System-on-Chip Test Architectures 2008
DOI: 10.1016/b978-012373973-5.50013-9
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Coping with Physical Failures, Soft Errors, and Reliability Issues

Laung Terng Wang
1
,
Mehrdad Nourani
2
,
T.M. Mak
3
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Cited by 1 publication
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