Coping with RC(L) interconnect design headaches

Pileggi, L.

doi:10.1109/iccad.1995.480019

Cited by 31 publications

(32 citation statements)

References 32 publications

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“…Accurate models for each wire segment and the driving gates are needed, which makes the overall interconnect network too complex to simulate. Therefore, recent developments try to improve the efficiency of timing verification while keeping the accuracy by using piecewise-linear models for gates and model-order reduction techniques for the interconnect network [37]. The complexity of the interconnect network can be reduced by techniques such as asymptotic waveform evaluation (AWE) [38] or related variants such as Padé via Lanczos (PVL), that use moment matching and Padé approximation to generate a lower order model for the response of a large linear circuit like an interconnect network.…”

Section: A Numerical Simulation Of Analog and Mixed-signal Circuitsmentioning

confidence: 99%

Computer-aided design of analog and mixed-signal integrated circuits

2000

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Section: A Numerical Simulation Of Analog and Mixed-signal Circuitsmentioning

confidence: 99%

Computer-aided design of analog and mixed-signal integrated circuits

2000

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“…Buffers are often inserted in long interconnect routes to reduce crosstalk noise [11]. Buffer insertion typically reduces crosstalk noise but sometimes degrades the performance due to the additional delays of the inserted buffers.…”

Section: Buffer Insertion Techniquementioning

confidence: 99%

“…But, with the recognized significance of including inductive effects and their impact on performance and signal integrity, several techniques have been proposed to deal with these effects. The most common of these techniques are: shielding [10] where signal lines are interdigitated with Vdd or ground alternatively in order to provide isolation of signal lines from their neighboring signals, and buffer insertion [11] where Manuscript received December 30, 2001; revised April 19, 2002. This work was supported by the Advanced Technology Group at Synopsys, the Somerset design center of Motorola, the DARPA packaging program, and the semiconductor research corporation.…”

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Expression of Concern: Managing on-chip inductive effects

Massoud

Majors²,

Kawa

et al. 2002

IEEE Trans. VLSI Syst.

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Abstract-With process technology and functional integration advancing steadily, chips are continuing to grow in area while critical dimensions are shrinking. This has led to the emergence of on-chip inductance to be a factor whose effect on performance and on signal integrity has to be managed by chip designers and has to be sometimes traded off against other performance parameters. In this paper, we cover several techniques to reduce on-chip inductance which in turn improve timing predictability and reduce signal delay and crosstalk noise. We present experimental results obtained from simulations of a typical high performance bus structure and a clock tree structure to examine the effectiveness of some of the different inductance reduction techniques.

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“…There are other variations on wire sizing optimizations, such as [12] for multiple-source nets, [13] and [14] for minimizing the maximum delay objective, and [15] and [16] considering high-order moments. Most of these studies, however, did not consider the coupling capacitance which becomes the dominant capacitance component in DSM designs.…”

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confidence: 99%

Wire width planning for interconnect performance optimization

Cong

Pan

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we study wire width planning for interconnect performance optimization in an interconnect-centric design flow. We first propose some simplified, yet near-optimal wire sizing schemes, using only one or two discrete wire widths. Our sensitivity study on wire sizing optimization further suggests that there exists a small set of "globally" optimal wire widths for a range of interconnects. We develop general and efficient methods for computing such a "globally" optimal wire width design and show rather surprisingly that using only two "predesigned" widths for each metal layer, we are still able to achieve close to optimal performance compared with that by using many possible widths, not only for one fixed length, but also for all wire lengths assigned at each metal layer. Our wire width planning can consider different design objectives and wire length distributions. Moreover, our method has a predictable small amount of errors compared with optimal solutions. We expect that our simplified wire sizing schemes and wire width planning methodology will be very useful for better design convergence and simpler routing architectures.

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Coping with RC(L) interconnect design headaches

Abstract: Abstract

Cited by 31 publications

References 32 publications

Computer-aided design of analog and mixed-signal integrated circuits

Computer-aided design of analog and mixed-signal integrated circuits

Expression of Concern: Managing on-chip inductive effects

Wire width planning for interconnect performance optimization

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