We show that that for a complex CLSI (1.4 A4 transistor; used in the Asymmetric Digital Subscriber Line product range}, 632 IDDQ measurements are needed to obtain 94% pseudo stuck-at fault coverage. The I'DQ test takes less than 200 ms on the VLSI test system, which is between 100 to 300 times faster compared to the use of a PMU. In addition, the OCIMU IDDQ monitor is built into our VLSI test system allowing IDDQ tests at wafer level without placing active components on the load board. This IDDQ methodology applies many IDDQ vectors, achieves a high fault coverage and is feasible in a production environment. Correlation between functional failures and IDDQ failures is around 70 %for three CLSI designs. Extrapolation implies that the slip-through (i.e. bad devices that pass all tests) can be reduced by 70 % by augmenting the test program with an IDDQ test. As a consequence, the non-quality costs can be reduced significantly depending on the slip-through figures, component and repair costs.