Copper Metal for Semiconductor Interconnects

Cheng, Yi-Lung; Lee, Chih-Yen; Huang, Yao-Liang

doi:10.5772/intechopen.72396

Cited by 19 publications

(15 citation statements)

References 159 publications

(172 reference statements)

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“…The model supposes a two-step calculation of spatial and time distributions for carrier densities. Firstly, we compute quantum-mechanical carrier densities n w and p w by the self-consistent solution of the Schrodinger-Poisson Equation system (1)(2)(3)(4)(5). At this step, finite difference coordinate and time grids are used, and the processes of carrier recombination and transport along the y axis are not taken into account.…”

Section: Numerical Modelmentioning

confidence: 99%

“…We apply two different systems of scaling factors. The first system given in Table 1 is designed for the normalization of the Schrodinger Equations (1), (2), and wavefunction boundary Condition (9). The second system represented in Table 2 is employed for the Poisson Equation 5and potential boundary Condition (10).…”

Section: Simulation Techniquementioning

confidence: 99%

“…The suggested approach reduces all physical constants in the Schrodinger and Poisson equations, but the normalization and denormalization procedures are carried out during each iteration of numerical calculations. (2), and (9).…”

Section: Simulation Techniquementioning

confidence: 99%

“…Traditional techniques of on-chip and chip-to-chip interconnecting are based on the application of metal conductors, which transmit signals by the charging and discharging of the whole wire. The degradation of metal interconnection characteristics in ultra-large-scale ICs (ULSIs) and other innovative integrated devices is an urgent scaling-related problem [2,3]. On the one hand, the downscaling of transistors leads to the miniaturization and more dense packing of localand intermediate-level wires in ULSIs and to the reduction in metallization step.…”

Section: Introductionmentioning

confidence: 99%

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Photodetector with Controlled Relocation of Carrier Density Peaks: Concept and Numerical Simulation

Pisarenko

Ryndin

2020

Photonics

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Modern electronics faces the degradation of metal interconnection performance in integrated circuits with nanoscale feature dimensions of transistors. The application of constructively and technologically integrated optical links instead of metal wires is a promising way of the problem solution. Previously, we proposed the advanced design of an on-chip injection laser with an AIIIBV nanoheterostructure, and a functionally integrated optical modulator. To implement the efficient laser-modulator-based optical interconnections, technologically compatible photodetectors with subpicosecond response time and sufficient sensitivity are required. In this paper, we introduce the concept of a novel high-speed photodetector with controlled relocation of carrier density peaks. The device includes a traditional p-i-n photosensitive junction and an orthogonally oriented control heterostructure. The transverse electric field displaces the peaks of electron and hole densities into the regions with low carrier mobilities and lifetimes during the back edge of an optical pulse. This relocation results in the fast decline of photocurrent that does not depend on the longitudinal transport of electrons and holes. We develop a combined numerical model based on the Schrodinger-Poisson equation system to estimate the response time of the photodetector. According to the simulation results, the steep part of the photocurrent back edge has a duration of about 0.1 ps.

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Section: Numerical Modelmentioning

confidence: 99%

Section: Simulation Techniquementioning

confidence: 99%

Section: Simulation Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Photodetector with Controlled Relocation of Carrier Density Peaks: Concept and Numerical Simulation

Pisarenko

Ryndin

2020

Photonics

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“…In general, any multilayered PCB consists of on-board conducting lines embedded on a dielectric medium, which reliably connects various electrical components such as resistors, capacitors, inductors, ICs, etc. For the conducting lines, copper (Cu) is the first choice for metallization because of its low resistivity, minimal electromigration, and high reliability [3,4].…”

Section: Introductionmentioning

confidence: 99%

Fabrication Process for On-Board Geometries Using a Polymer Composite-Based Selective Metallization for Next-Generation Electronics Packaging

2021

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Advancements in production techniques in PCB manufacturing industries are still required as compared to silicon-ICs fabrications. One of the concerned areas in PCBs fabrication is the use of conventional methodologies for metallization. Most of the manufacturers are still using the traditional Copper (Cu) laminates on the base substrate and patterning the structures using lithography processes. As a result, significant amounts of metallic parts are etched away during any mass production process, causing unnecessary disposables leading to pollution. In this work, a new approach for Cu metallization is demonstrated with considerable step-reducing pattern-transfer mechanism. In the fabrication steps, a seed layer of covalent bonded metallization (CBM) chemistry on top of a dielectric epoxy resin is polymerized using actinic radiation intensity of a 375 nm UV laser source. The proposed method is capable of patterning any desirable geometries using the above-mentioned surface modification followed by metallization. To metallize the patterns, a proprietary electroless bath has been used. The metallic layer grows only on the selective polymer-activated locations and thus is called selective metallization. The highlight of this production technique is its occurrence at a low temperature (20–45 °C). In this paper, FR-4 as a base substrate and polyurethane (PU) as epoxy resin were used to achieve various geometries, useful in electronics packaging. In addition, analysis of the process parameters and some challenges witnessed during the process development are also outlined. As a use case, a planar inductor is fabricated to demonstrate the application of the proposed technique.

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