CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study

Abstract

Ahstract-Multiprocessor System-on-Chip (MPSoC) is an in tegral element in state-of-the-art embedded devices, ranging from low-end, mobile phones, PDAs, handheld medical devices up to high-end cars, avionics and robotics. Proper and safe functionality of such embedded systems is mandatory to avoid severe consequences, whereas security is absolutely necessary with "Cashless Wallets" forecasted to be the only means of financial transactions in the near future. Such a scenario places immense onus on the security experts where secure transactions using credit cards or mobile phones or any other embedded devices should not be revealing any footprint to the adversary. Side Channel Attacks (SCA) are considered as one of the most effective attacks on these embedded systems because of their effectiveness in realizing the secret information without physically disassembling the device. We propose an MPSoC architecture to prevent power analysis SCA where a dual-core algorithmic balancing is enforced by corrupting the balanced key and swapping the encryption rounds of a block-cipher at random places, random number of times. A case study using DES cryptography is performed. Our approach, CoRaS, alleviates performance by 0.1 % and area by 3.6% compared to the state-of-the-art MPSoC solution, however enhances security and practicality by eliminating its weaknesses.

SecureD: A Secure Dual Core Embedded Processor

“…However, this could be a challenging task and would require manual design considerations. We could use the CoRaS solution [4] to counteract this limitation by randomly swapping rounds of the encryption/decryption between processors.…”

Side channel attacks in embedded systems: A tale of hostilities and deterrence

“…A similar algorithmic balancing approach is proposed in [49] for AES but executed using a Multiprocessor System-onChip (MPSoC). In order to further confuse the adversary, Ambrose et al [50] proposed the randomization of the execution of AES rounds by swapping the balanced code between processors in an MPSoC.…”