Core-Selectability in Chip Multiprocessors

Abstract

The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip multiprocessors (CMP). The reason for this is that scaling these structures does not enhance general performance as much as scaling the cache and interconnect. However, the fact that these structures now consume less proportional die area opens an avenue to enhancing their performance through truly overcoming the one-size-fits-all approach to their design. This paper proposes core-selectability -incorporating differently-designed cores that can be toggled into active employment. This enables differently customized ILP-extracting structures to be at hand in the system while not dramatically adding to the interconnect complexity. The design verification effort is minimized by separating the complexity of different core designs. Moreover, contrary to alternative approaches, the performance and power efficiency of the core designs are not compromised. Evaluation results are presented that show that, even when limiting the diversity between core designs to only the sizing of microarchitectural structures, core-selectability has the potential to provide notable performance enhancement (with an average of 10%) to scalable multithreaded applications, without increased concurrency. In addition, it can provide significantly greater throughput to multiprogrammed workloads by providing the potential for the system to transform into a heterogeneous design.

Heterogeneous microarchitectures trump voltage scaling for low-power cores

“…Cache sharing solutions rely on multiplexing the L1 caches between multiple cores to eliminate much of the state transfer overheads when switching [29,32]. Other researchers have proposed multiplexing pipeline stages between cores to achieve heterogeneity [30].…”

Implications of the Power Wall: Dim Cores and Reconfigurable Logic

“…We also assume that the serial core is gated off in parallel mode to save power for throughput-oriented dim cores. We study both conventional out-of-order core, such as Core i7, as well as core-selectability [12]. We find that even with an embarrassingly parallel application, the die area investment on a dedicated O3 core is still beneficial.…”

Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores

“…In [32], Gibson et al propose a forward flow architecture where the execution logic can be scaled to meet the requirements of the incoming workloads. In [9], Najaf-abadi et al propose core selectability where each "node" in the system consists of different types of cores that share common resources. Depending on the application, the respective core from the node is selected to serve that application.…”

“…Recent studies have shown that symmetric cores are unlikely to provide better performance than a heterogeneous multicore [13], [18]. Further studies [9], [16], [18], [33], [36] have shown that reconfigurable architectures may increase the benefits of AMPs even further. This provides a strong argument for our target multicore architecture.…”