Correction to Ultracompliant Heterogeneous Copper–Tin Nanowire Arrays Making A Supersolder

Gong, Wei; Li, Pengfei; Zhang, Yunheng; Feng, Xuhui; Major, Joshua; DeVoto, Douglas; Paret, Paul; King, Charly; Narumanchi, Sreekant; Shen, Sheng

doi:10.1021/acs.nanolett.8b02425

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“…Advanced device integration technologies, such as surface mounting, through-silicon-via filling, and flip–chip bonding, are bridges linking subcomponents, providing electrical conduction, mechanical reliability, and heat dissipation for electronic systems. In recent years, the electronic industry is witnessing a slowing down on feature-size scaling.…”

Section: Introductionmentioning

confidence: 99%

Cooperative Bilayer of Lattice-Disordered Nanoparticles as Room-Temperature Sinterable Nanoarchitecture for Device Integrations

Feng

Shen

Wang

et al. 2019

ACS Appl. Mater. Interfaces

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Decreasing the interconnecting temperature is essential for 3D and heterogeneous device integrations, which play indispensable roles in the coming era of “more than Moore”. Although nanomaterials exhibit a decreased onset temperature for interconnecting, such an effect is always deeply impaired because of organic additives in practical integrations. Meanwhile, current organic-free integration strategies suffer from roughness and contaminants at the bonding interface. Herein, a novel bilayer nanoarchitecture simultaneously overcomes the drawbacks of organics and is highly tolerant to interfacial morphology, which exhibits universal applicability for device-level integrations at even room temperature, with the overall performance outperforming most counterparts reported. This nanoarchitecture features a loose nanoparticle layer with unprecedented deformability for interfacial gap-filling, and a compact one providing firm bonding with the component surface. The two distinct nanoparticle layers cooperatively enhance the interconnecting performance by 73–357%. Apart from the absence of organics, the internal abundant lattice disorders profoundly accelerate the interconnecting process, which is supported by experiments and molecular dynamics simulation. This nanoarchitecture is successfully demonstrated in diversified applications including paper-based light-emitting diodes, Cu–Cu micro-bonding, and SiC power modules. The strategy proposed here can open a new paradigm for device integrations and provide a fresh understanding on interconnecting mechanisms.

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Section: Introductionmentioning

confidence: 99%

Cooperative Bilayer of Lattice-Disordered Nanoparticles as Room-Temperature Sinterable Nanoarchitecture for Device Integrations

Feng

Shen

Wang

et al. 2019

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

show abstract

Correction to Ultracompliant Heterogeneous Copper–Tin Nanowire Arrays Making A Supersolder

Abstract: The following should be added to the end of the Acknowledgment: The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government.

Cited by 1 publication

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Cooperative Bilayer of Lattice-Disordered Nanoparticles as Room-Temperature Sinterable Nanoarchitecture for Device Integrations

Cooperative Bilayer of Lattice-Disordered Nanoparticles as Room-Temperature Sinterable Nanoarchitecture for Device Integrations

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