Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design

Abstract

High-level synthesis (HLS) tools have gained great attention in recent years because it emancipates engineers from the complicated and heavy hardware description language writing and facilitates the implementations of modern applications (e.g., deep learning models) on Field-programmable Gate Array (FPGA) , by using high-level languages and HLS directives. However, finding good HLS directives is challenging, due to the time-consuming design processes, the balances among different design objectives, and the diverse fidelities (accuracies of data) of the performance values between the consecutive FPGA design stages. To find good HLS directives, a novel automatic optimization algorithm is proposed to explore the Pareto designs of the multiple objectives while making full use of the data with different fidelities from different FPGA design stages. Firstly, a non-linear Gaussian process (GP) is proposed to model the relationships among the different FPGA design stages. Secondly, for the first time, the GP model is enhanced as correlated GP (CGP) by considering the correlations between the multiple design objectives, to find better Pareto designs. Furthermore, we extend our model to be a deep version deep CGP (DCGP) by using the deep neural network to improve the kernel functions in Gaussian process models, to improve the characterization capability of the models, and learn better feature representations. We test our design method on some public benchmarks (including general matrix multiplication and sparse matrix-vector multiplication) and deep learning-based object detection model iSmart2 on FPGA. Experimental results show that our methods outperform the baselines significantly and facilitate the deep learning designs on FPGA.

Multi-fidelity cost-aware Bayesian optimization

“…As stated in Chapter 1, the overall computational efficiency of BO can be increased by leveraging inexpensive LF datasets. MF BO has been successfully used in many applications such as hyperparameter tuning [43,44,45,46], finding Pareto fronts in multi-objective optimizations [47,48,49], and solving non-linear state-space models [50,51]. For MFBO, both the emulator and the AF must accommodate the multi-source and unbalanced 7 nature of the data.…”

A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor

“…Additionally, the customized ISA still has room for optimization considering the software code design and hardware component cost. Related researches on design space exploration for microarchitecture have also emerged in recent years [17,19,21,22,23]. The BOOM-Explorer [19] is an microarchitecture design space exploration framework for tuning the RISC-V BOOM implementation, for instance, the implementation parameters of different hardware modules.…”

The shift-left design paradigm of EDA: progress and challenges

“…清华 大学还提出通过强化学习的方法, 实现在模拟电路设计阶段将工艺信息融合 [10] . 香港中文大学提出基 于图神经网络技术的功耗估计方法, 进而辅助高层次综合阶段的设计空间探索 [11] . 香港中文大学还提 出在设计早期将时序信息融入斯坦纳 (Steiner) 点的调整, 以及将多重曝光信息融入标准单元设计中, 从而提升设计质量 [12,13] .…”