Correlation of logical failures to a suspect process step

Abstract

1 I Traditional yield enhancement efforts have long relied on memory bibnapping techniques. With the industry marching toward system-on-a-chip technology, the importance bf logic products has increased exponentially. This necessitates the development of innovative techniques io perform logic yield enhancement. In this paper, the authors present a novel technique that can be used to peaorm logic yield enhancement. The paper concentrates on logic bitmapping at Texas Instruments. Results obtained from a few production samples of a graphics processor are also presented.

A Survey of Yield Modeling and Yield Enhancement Methods

“…Similarly, in [72], [73], logic diagnosis data is overlayed with in-line inspection to identify killer defects in logic. The problem of linking electrical test failures to in-line defects was found to be very challenging, not just because the number of nets identified by an automated diagnosis tool as suspect candidates was often high, but also because a single net can spread across the entire surface of a die.…”

Modeling Test Escape Rate as a Function of Multiple Coverages

“…Obviously, the level of detection overlap will vary depending on the nature of the defect and the types of tests applied. Figure 3 shows various typical resistive open and bridging defects from early 90nm development that were observed in the logic defect Pareto from parts failing production stuck-at patterns using Logic Mapping [35]. Other factors are more design-centric, such as the amount of timing or voltage margin incorporated into the design combined with the aggressiveness of the corresponding tests, or the background leakage of the library elements and the type of I DDQ testing being employed.…”

Implementation Update: Logic Mapping On SPARC- Microprocessors

“…Since its introduction, Logic Mapping has only been documented on a few industrial products, primarily as an engineering tool on a limited amount of material [1][2][3][4][5][6]. In the previous work by these authors [7] there was proof of the potential value of Logic Mapping.…”

“…

Despite the initial proof of concept being completed almost a decade ago [1], the production implementations of Logic Mapping have taken significantly longer. This paper presents an update for the SPARC™ Microprocessors, along with a discussion of some production worthiness metrics and methods applied to overcome issues on these designs.

…”