“…Among them, however, the influence of the side wall roughness, the line edge roughness (LER) or the line width roughness (LWR), to CDs has rarely been included in a theoretical calculation because of the complexity of constructing a reasonable rough surface model. The LER or the LWR can degrade resolution and linewidth accuracy (Yoshimura et al, 1993) and cause fluctuation of transistor performance (Asenov et al, 2003;Croon et al, 2002;Diaz et al, 2001;Ercken et al, 2002;Hamadeh et al, 2006;Kaya et al, 2001;Kim et al, 2004a;Kim et al, 2004b;Linton et al, 1999;Linton et al, 2002;Oldiges et al, 2000;Xiong & Bokor, 2002;Yamaguchi et al, 2003;Yamaguchi et al, 2004). It becomes a critical issue when the CDs for semiconductor devices shrink into few tens nanometers (ITRS, 2007;Gwyn et al, 2003) because the roughness on the edge of the line does not scale with the linewidth (Asenov et al, 2003).…”