Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration

Abstract

Due to the increasing fabrication and design complexity with new process nodes, the cost per transistor trend originally identified in Moore's Law is slowing when using traditional integration methods. However, emerging die-level integration technologies may be viable alternatives that can scale the number of transistors per integrated device while reducing the cost per transistor through yield improvements across multiple smaller dies. Additionally, the escalating overheads of non-recurring engineering costs like masks and verification can be curtailed through die integration-enabled reuse of intellectual property across heterogeneous process technologies. In this paper, we present an analytical cost model for 3D and interposer-based 2.5D die integration and employ it to demonstrate the potential cost reductions across semiconductor markets. We also propose a methodology and platform for IP reuse based on these integration technologies and explore the available reductions in overall product cost through reduction in non-recurring engineering effort.

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

“…Interposer stacks are a widely accepted, cost-efficient alternative to 3D ICs [8], [16], [17], [18], [19], [20], [21], [22]. Here, active dies are arranged in lateral direction on a substrate-possibly on both of its sides-instead of stacking them strictly vertically.…”

“…As for homogeneous digital integration, interposer enable the partitioning of a large monolithic die (with low yield) into smaller dies (with higher yield) [19], [22]. This greatly lowers the overall manufacturing cost and also helps to improve the power efficiency.…”

“…A key observation is that most challenges can be eased once system-level 3D integration (of 2D chips) is pursued. The related concept of interposer-based 3D integration is widely accepted nowadays [8], [16], [17], [18], [19], [20], [21], [22]; it is a practical, flexible, and cost-effective alternative to the previously more anticipated full-custom and native 3D integration.…”

Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse

“…Before applying 2.5D technology to real designs, a thorough analysis of trade-offs between monolithic 2D SoC and interposerbased 2.5D design should be preceded. There are existing studies on 2.5D IC design focused on the design methodology or utility point of view such as analysis of design cost aspect [5] and bump Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored.…”

“…(3) We propose a new logical protocol that is well fitted for 2.5D IC design; (4) We analyze PPA of 2.5D ICs using different interposer technologies to show overhead difference; (5) We analyze PPA of interposer-based 2.5D ICs and compare the result with monolithic 2D IC to investigate overheads of 2.5D design. To our best knowledge, this is the first work to fully quantify the design gap between 2D and 2.5D designs in terms of PPA using GDS layouts and sign-off simulations.…”