Cost Comparison of 2.5D/3D Packaging to other Packaging Technologies

Abstract

2.5D and 3D applications using through silicon vias (TSVs) are increasingly being considered as an alternative to conventional packaging. Miniaturization and high performance product requirements are driving this move, although in many cases the cost of both 2.5D and 3D is still high. In this paper we will identify the major cost drivers for 2.5D and 3D packaging and assess cost reduction progress, including current costs versus expected future costs. We will also compare these costs to alternative packaging.

3D system-on-a-chip design with through-silicon-via-less power supply using highly doped silicon via

“…While TSV needs an additional costly process and new wafer logistics to form through electrodes, HDSV requires only implantation and an annealing process in the same fab, which leads to cost reduction. [23][24][25] Whereas the 3D integration with TSV costs 23% of its wafer cost, 26) the 3D integration with the N-HDSV requires 7% since it needs only one additional mask, where 5% comes from the additional wafer cost with the longer annealing time taken into account and 2% 27) is for the 3D integration similar to the TSV's case. Though the resistance of HDSV is higher than that of TSV, it is still low enough as will be discussed in Sects.…”