Cost comparison of image rotation implantations on static and dynamic Reconfigurable FPGAs

Bourennane, El-Bay; Bouchoux, Sophie; Mitéran, Johel; Paindavoine, Michel; Bouillant, S.

doi:10.1109/icassp.2002.5745324

Cited by 2 publications

(7 citation statements)

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“…The motivation behind this thesis is to provide the embedded reconfigurable engineering community with an approach that will help guide hardware design engineers in determining the correct and most appropriate computing architecture design for a particular reconfigurable region allocated for a specific application in a Dynamic Partially Reconfigurable Computing System(DPRCS). Currently the most widely explored approaches involve the use of performance [1], power [2], area [3], and resources [4] for analysis of various computing systems.…”

Section: Also Would Like To Thank the Department Of Electrical And Computer Engineering At Ryersonmentioning

confidence: 99%

“…Test the proposed approach by implementation of dedicated hardware components, hybrid components and software based components. 4. Analyze the results from the two test experiments.…”

Section: Objectivesmentioning

confidence: 99%

“…Software and Hybrid computing architecture implementation for two test applications. 4. Computing Architecture design and Implementation of the Natural User Interface Augmented Reality Display System (NUI-ARDS).…”

Section: Original Contributionsmentioning

confidence: 99%

“…The CEF for a complex design and implementation of an industrial application involving 3D stereo panoramic video streaming with augmented reality and remote robotic agent control system is determined. 4. Chapter 5 discusses the results and the implications CEF can have in the design of dynamic partially reconfigurable computing systems.…”

Section: Thesis Organizationmentioning

confidence: 99%

“…In order to take advantage of all three computing architectures one can use [7] a dynamic reconfigurable computing architecture (DRCA) depicted in Figure 2. 4. This type of computing architecture usually consists of two sections: a static section and a dynamic (Reconfigurable) section.…”

Section: Related Work Observation and Analysismentioning

confidence: 99%

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A Cost Efficiency Analysis and Mechanism for Dynamic Partially Reconfigurable Computing Systems

Díaz¹

2021

Preprint

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Dynamic Partially Reconfigurable Computing Systems have proven to be useful in environments where a multiplicity of tasks is required. These systems used Dynamic Virtual Components (DVCs) for reconfiguration. However, the computing architecture (dedicated, software, hybrid) of the DVC must be selected during the design stage. In this thesis, a mechanism in which we evaluate and analyze the cost efficiency of a DVC based on a cost efficiency factor (CEF) is proposed. Data centric and stream centric experimental tests were performed and the CEF of a 3D stereo-panoramic augmented reality hybrid DVC was de termined. The results show that development costs and number of units to be produced influence the cost efficiency of a DVC. From the results it is concluded that the CEF can be a useful tool for selecting the computing architecture of a DVC, particularly when only a few units are to be deployed.

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Section: Also Would Like To Thank the Department Of Electrical And Computer Engineering At Ryersonmentioning

confidence: 99%

“…Test the proposed approach by implementation of dedicated hardware components, hybrid components and software based components. 4. Analyze the results from the two test experiments.…”

Section: Objectivesmentioning

confidence: 99%

Section: Original Contributionsmentioning

confidence: 99%

Section: Thesis Organizationmentioning

confidence: 99%

Section: Related Work Observation and Analysismentioning

confidence: 99%

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A Cost Efficiency Analysis and Mechanism for Dynamic Partially Reconfigurable Computing Systems

Díaz¹

2021

Preprint

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Implementation of Multi-Core Processor for Beamforming Algorithm of Mobile Ultrasound Image Signals

Choi¹,

Kim²

2011

The KIPS Transactions:PartA

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In the past, a patient went to the room where an ultrasound image diagnosis device was set, and then he or she was examined by a doctor. However, currently a doctor can go and examine the patient with a handheld ultrasound device who stays in a room. However, it was implemented with only fundamental functions, and can not meet the high performance required by the focusing algorithm of ultrasound beam which determines the quality of ultrasound image. In addition, low energy consumption was satisfied for the mobile ultrasound device. To satisfy these requirements, this paper proposes a high-performance and low-power single instruction, multiple data (SIMD) based multi-core processor that supports a representative beamforming algorithm out of several focusing methods of mobile ultrasound image signals. The proposed SIMD multi-core processor, which consists of 16 processing elements (PEs), satisfies the high-performance required by the beamforming algorithm by exploiting considerable data-level parallelism inherent in the echo image data of ultrasound. Experimental results showed that the proposed multi-core processor outperforms a commercial high-performance processor, TI DSP C6416, in terms of execution time (15.8 times better), energy efficiency (6.9 times better), and area efficiency (10 times better).

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Cost comparison of image rotation implantations on static and dynamic Reconfigurable FPGAs

Cited by 2 publications

References 8 publications

A Cost Efficiency Analysis and Mechanism for Dynamic Partially Reconfigurable Computing Systems

A Cost Efficiency Analysis and Mechanism for Dynamic Partially Reconfigurable Computing Systems

Implementation of Multi-Core Processor for Beamforming Algorithm of Mobile Ultrasound Image Signals

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