Cost-effective accurate DAC-ADC co-testing and DAC linearization

Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs

“…Authors demonstrate that an 8-bit DAC with the proposed DDEM strategy can be used for testing a 12-bit ADC. The work in [13], [14] uses a DAC-ADC loopback configuration in which the effective resolution of DAC and ADC are raised by appropriately scaling and shifting the output of the DAC. The use of segmented resistor-string DACs as an on-chip static stimulus generator has been explored in [15].…”

“…It is important to notice that |∆C i /C F | should be minimized in order to ensure that the nominal step size of the ramp is larger than the contribution of the mismatch in (14). That is, for a practical ramp generator it has to be verified that…”

“…These results were obtained by simulating a Matlab behavioral model of the generator in Fig. 1 under capacitor mismatch conditions, based on the analytical behavior in equation (14). As it is clearly shown in Fig.…”

“…For a fair comparison, it has to be noted that each of the measurement techniques in Table VI is aimed at a different target application. Thus, the works in [5], [11], [13] are aimed at static linearity BIST applications of ADCs using embedded signal generators, while the measurement strategies in [18]- [21], [24], [25] rely on external equipment and dedicated post-processing to either relax the linearity requirement of the signal generator [14], [18]- [20], reduce the number of necessary measurements [21], [25], or both [24], [27]. The work presented in this manuscript is aimed at BIST applications, and, as it is shown in Table VI, the obtained experimental results compare very well to the state-of-the-art.…”

“…In this line, the target application defines the type of tests required for the ADCs in the system. Thus, On-chip signal generator based on current source integration Simulation 10 bit ±0.03 LSB (DNL) [5] On-chip signal generator based on relaxation oscillator Simulation 10 bit ±0.15 LSB (DNL) [11] On-chip signal generator based on low-resolution DAC with DDEM Experimental 11 bit ±0.5 LSB [11] On-chip signal generator based on low-resolution DAC with DDEM Experimental 12 bit ±1 LSB [13] ADC/DAC loopback test Experimental 10 bit ±0.4 LSB [14] DAC-ADC co-testing Simulation 12 bit ±0.5 LSB [20] Low resolution DAC with polynomial fitting algorithm Experimental 12 bit ±0.6 LSB [18] Stimulus error identification and removal Experimental 16 bit ±2 LSB [27] Error identification and segmented model identification Simulation 16 bit ±0.8 LSB [19] Double histogram strategy Simulation 16 bit ±1 LSB [21] Reduced code linearity testing of pipeline ADCs Experimental 11 bit ±0.2 LSB [25] Transition-code linearity test of pipeline ADCs Experimental 12 bit ±1.1 LSB [24] Code-density testing with non-linearity identification and removal Experimental 16 bit ±1 LSB as it is described in [3], static performance is critical for applications such as automatic control and data acquisition, while dynamic performance is critical for audio applications. Imaging applications, on the other hand, demand both static and dynamic tests for an appropriate characterization.…”