Cost-effective decap selection for beyond die power integrity

Abstract

1 Abstract-In designing reliable power distribution networks (PDN) for power integrity (PI), it is essential to stabilize voltage supply to devices on chip. We usually employ decoupling capacitor (decap) to suppress the noise generated by the switching of devices. There have been numerous prior works on how to select/insert decaps in chip, package, or board to maintain PI, however optimal decap selection is usually not applicable due to design budget and manufacturability. Moreover, design cost is seldom touched or mentioned. In this research, we propose an efficient methodology "PDC-PSO" to automatically optimizing the selection of available decaps. This algorithm not only takes advantage of particle swarm optimization (PSO) to stochastically search the design space, but takes the most effective range of decaps into consideration to outperform the basic PSO. We apply this to three real package designs and the results show that, compared to the original decap selection by rules of thumb, our approach could shorten the design period and we have better combination of decaps at the same or lower cost. In addition, our methodology can also consider package-board co-design in optimizing different operation frequencies.

Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems

“…However, this is an optimistic method because it is difficult to predict the PI due to parasitic capacitance and the inductance at high frequency in real PDSs. Chen et al [24] implemented a memory controller hub and dynamic random-access memory modules to generate a current profile. However, creating a current profile through a memory module design is also difficult for the same reason as that for CPM.…”