Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines

Deb, Dipika; Jose, John; Das, Shirshendu; Kapoor, Hemangee K.

doi:10.1016/j.jpdc.2018.09.009

Cited by 23 publications

(9 citation statements)

References 23 publications

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“…It does it by selectively dropping data by measuring with the qualitative model. A back pressure-based work is presented by Deb et al [31] that focuses on reducing hop count by utilizing a longdistance transmission line. They propose SBTR and e-SBTR router architectures.…”

Section: ) Congestion Propagation Network -Using Dedicated Wirementioning

confidence: 99%

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

et al. 2022

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Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. Network-on-Chip (NoC) is a scalable and promising interconnection solution used by MPSoCs to achieve high performance. Routing algorithms provide a path to a packet toward the destination. For this, these algorithms should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews the selection strategies used to reduce congestion in NoC and classifies them on the technique adopted to handle and propagate congestion information. Additionally, this paper provides the implementation and analysis details of some state-of-art selection methods.

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Section: ) Congestion Propagation Network -Using Dedicated Wirementioning

confidence: 99%

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

et al. 2022

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“…After calculating the length and direction, it is necessary to determine which of the generators is required to take a hop. Trivial choice is in the case when the distance is divided by one of the generators without a residue (3). From this, it follows that it is necessary to choose the next vertex, based on the sum or difference of index of the current node and value of the selected generator.…”

Section: Description Of the Routing Algorithm For Cðn; D; D þ1þ Circumentioning

confidence: 99%

“…In particular, it is the topology that has a significant impact on NoC performance. The most common are classical regular topologies such as mesh [3] and torus [4], which do not always meet modern requirements for NoCs, especially with an increase in the number of nodes [5]. Different researchers suggest other topology options among which we can distinguish hypercube [6,7,8], chordal ring [9,10], spidergon [11], L-networks [12].…”

Section: Introductionmentioning

confidence: 99%

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

Romanov

Lezhnev

Glukhikh

et al. 2020

Heliyon

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This work is devoted to the study of application of new topologies in the design of networks-on-chip (NoCs). It is proposed to use two-dimensional optimal circulant topologies for NoC design, and it is developed an optimized routing algorithm with the decreased memory usage. The proposed routing algorithm was compared with Table routing, Clockwise routing, and Adaptive routing algorithms, previously developed for ring circulant topologies, and specialized routing algorithm for multiplicative circulants. The results of synthesis of routers implementing proposed routing algorithms are presented. The cost of ALM and register resources for the implementation of communication subsystems in NoCs with circulant topologies is estimated.

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“…New classes and families of such optimal structures are constructed on the basis of both regular [ 7 , 8 , 9 ] and irregular [ 10 ] network topologies. The NoC topology itself has a decisive influence on NoC performance [ 11 , 12 ].…”

Section: Introductionmentioning

confidence: 99%

Routing in triple loop circulants: A case of networks-on-chip

Romanov

Starykh

2020

Heliyon

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In this paper we propose and analyze various approaches to organizing routing in a triple loop circulant topologies as applied to networks-on-chip: static routing based on universal graph search algorithms, such as Dijkstra's algorithm and a possible implementation using Table routing; algorithms created analytically based on an engineering approach with taking into account the structural features of triple loop circulant graphs (Advanced clockwise, Direction selection); an algorithm created on the basis of a mathematical analysis of graph structure and solving the problem of enumerating coefficients at generators (Coefficients finding algorithm). Efficiency, maximum graph paths, occupied memory resources, and calculation time of the algorithms developed are estimated. Comparison of various variants of the algorithms is made and recommendations on their application for the development of networks-on-chip with triple loop circulant topologies are given. It is shown that Advanced clockwise and Direction selection algorithms guarantee that the packet reaches the destination node, but often in more steps than the shortest path. Nevertheless, they themselves are simpler and require less hardware resources than other algorithms. In turn, Coefficients finding algorithm has great computational complexity, but is optimal and, in comparison with Dijkstra's algorithm, is much simpler for RTL implementation which reduces network-on-chip routers resources cost.

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Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines

Cited by 23 publications

References 23 publications

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs

Development of routing algorithms in networks-on-chip based on two-dimensional optimal circulant topologies

Routing in triple loop circulants: A case of networks-on-chip

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