Cost-effective smart memory implementation for parallel backprojection in computed tomography

Abstract

Abstract-As nanoscale lithography challenges mandate greater pattern regularity and commonality for logic and memory circuits, new opportunities are created to affordably synthesize more powerful smart memory blocks for specific applications.Leveraging the ability to embed logic inside the memory block boundary, we demonstrate the synthesis of smart memory archi tectures that exploits the inherent memory address patterns of the backprojection algorithm to enable efficient parallel image reconstruction at minimum hardware overhead. An end-to end design framework in sub-20nm CMOS technologies was constructed for the physical synthesis of smart memories and evaluation of the huge design space. Our experimental resultsshow that customizing memory for the computerized tomogra phy (CT) parallel backprojection can achieve more than 30% area and power savings while offering significant performance improvements with marginal sacrifice of image accuracy.

Performance evaluation of SD – cards by "system-on-chip" technology

“…Мировые лидеры в области производства памяти продолжают развивать не только сегмент своих высокоскоростных SD-накопителей и жестких дисков, но и доступные и быстрые накопители для мобильного хранения данных -быстрые карты памяти и флэш-памяти больших размеров, предназначен-ные для применения в портативных и миниатюрных устройствах, таких как мобильный телефон, цифро-вой фотоаппарат и пр. [3][4][5][6].…”