Cost-efficient memory architecture design of NAND flash memory embedded systems

Park, C.; Seo, Jae M.; Seo, Dong Il; Kim, S.; Kim, B.

doi:10.1109/iccd.2003.1240943

Cited by 39 publications

(24 citation statements)

References 5 publications

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“…The critical path of the NV microcontroller is generally a read-path of NV memory. This is because NV memory is slower than that of the other logic types [11]. In addition, operation frequency is determined by the critical path Figure 11.…”

Section: Area and Critical Pathmentioning

confidence: 99%

“…In most cases, the increased delay time of the cache hit determination will not exceed the existing critical path of the NV microcontroller (read-path of NV memory). In most cases, the delay time of the NV memory read-path is higher than that of the logic path [11]. However, if the increased delay time of the logic path by cache hit determination exceeds the existing critical path, the delay time of the critical path will increase up to 2.91 ns for a 1-word-perline instruction cache, and 3.62 ns for a 4-word-per-line instruction cache.…”

Section: Area and Critical Pathmentioning

confidence: 99%

See 1 more Smart Citation

Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache

Kim¹,

Hida²,

Fukuda³

et al. 2014

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Demands for low-energy microcontrollers have been increasing in recent years. Since most microcontrollers achieve user programmability by integrating nonvolatile (NV) memories such as flash memories for storing their programs, the large power consumption required in accessing an NV memory has become a major problem. This problem becomes critical when the power supply voltage of NV microcontrollers is decreased. We can solve this problem by introducing an instruction cache, thus reducing the access frequency of the NV memory. Unlike general-purpose microprocessors, microcontrollers used for real-time applications in embedded systems must accurately calculate program execution time prior to its execution. Therefore, we introduce a "transparent" instruction cache, which does not change the existing NV microcontroller's cycle-level execution time, for reducing power and energy consumption, but not for improving the processing speed. We have conducted detailed microar chitecture design based on the architecture of a major industrial microcontroller, and we evaluated power and energy consumption for several benchmark programs. Our evaluation shows that the proposed instruction cache can successfully reduce energy consumption in a fairly wide range of practical NV microcontroller configurations.

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Section: Area and Critical Pathmentioning

confidence: 99%

Section: Area and Critical Pathmentioning

confidence: 99%

Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache

Kim¹,

Hida²,

Fukuda³

et al. 2014

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“…[15] showed that adding SRAM buffers to NAND flash can provide XiP. Otherwise, code in NAND flash must be loaded to main memory for execution.…”

Section: Related Workmentioning

confidence: 99%

Demand code paging for NAND flash in MMU-less embedded systems

Baiocchi

Childers

2011

2011 Design, Automation &Amp; Test in Europe

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Abstract-NAND flash is preferred for code and data storage in embedded devices due to its high density and low cost. However, NAND flash requires code to be copied to main memory for execution. In inexpensive devices without hardware memory management, full shadowing of an application binary is commonly used to load the program. This approach can lead to a high initial application start-up latency and poor amortization of copy overhead. To overcome these problems, we describe a software-only demand-paging approach that incrementally copies code to memory with a dynamic binary translator (DBT). This approach does not require hardware or operating system support. With careful management, a savings can be achieved in total code footprint, which can offset the size of data structures used by DBT. For applications that cannot amortize full shadowing cost, our approach can reduce start-up latency by 50% or more, and improve performance by 11% on average.

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“…Note that, most flash-based and/or disk-based previous researches also conducted a trace-driven simulation to verify their performance [24][25][26]. Especially, we want to verify that the caused overhead during normal operations is acceptable although it depends on DoI.…”

Section: Performance Evaluationsmentioning

confidence: 99%

Recovery of Flash Memories for Reliable Mobile Storages

Moon

Park

Chung

et al. 2010

Mobile Information Systems

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Abstract.As the mobile appliance is applied to many ubiquitous services and the importance of the information stored in it is increased, the security issue to protect the information becomes one of the major concerns. However, most previous researches focused only on the communication security, not the storage security. Especially, a flash memory whose operational characteristics are different from those of HDD is used increasingly as a storage device for the mobile appliance because of its resistance to physical shock and lower power requirement. In this paper, we propose a flash memory management scheme targeted for guaranteeing the data integrity of the mobile storage. By maintaining the old data specified during the recovery window, we can recover the old data when the mobile appliance is attacked. Also, to reduce the storage requirement for the recovery, we restrict the number of versions to be copied, called Degree of Integrity (DoI). Especially, we consider both the reclaim efficiency and the wear leveling which is a unique characteristic of the flash memory. Based on the performance evaluation, we confirm that the proposed scheme can be acceptable to many applications as a flash memory management scheme for improving data integrity.

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Cost-efficient memory architecture design of NAND flash memory embedded systems

Cited by 39 publications

References 5 publications

Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache

Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache

Demand code paging for NAND flash in MMU-less embedded systems

Recovery of Flash Memories for Reliable Mobile Storages

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