Cost-efficient QCA reversible combinational circuits based on a new reversible gate

Chabi, Amir Mokhtar; Roohi, Arman; DeMara, Ronald F.; Angizi, Shaahin; Navi, Keivan; Khademolhosseini, Hossein

doi:10.1109/cads.2015.7377779

Cited by 28 publications

(11 citation statements)

References 19 publications

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“…In this work three multiplexer designs, design-I, design-II, and design-III are implemented using QCA [4], SAM [10], and QCA & SAM reversible logic gates respectively. In addition, two demultiplexer designs, design-I and design-II are implemented using RAMESH and RAMESH-1 reversible logic gates respectively.…”

Section: Resultsmentioning

confidence: 99%

“…A.M Chabi and Arman Roohi et.al, designed QCA reversible logic gate and implemented XOR gate and 2:1 multiplexer. These designs achieved less area and power consumption [4]. Neha Pannu and Neelam Rup Prakash, implemented multiplexer using FREDKIN reversible logic gate.…”

Section: Literature Surveymentioning

confidence: 99%

“…In this work three multiplexer designs are implemented using two reversible logic gates QCA [4], SAM [10] and combination of both the gates. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1.…”

Section: Literature Surveymentioning

confidence: 99%

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Novel design of multiplexer and demultiplexer using reversible logic gates

Nune¹,

R²

2018

IJET

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Reversibility is the prominent technology in the recent era. In reversible logic the number output lines are equal to the number of input lines. In reversible logic the inputs are to be retrieved from the outputs. Reversible logic gates are user defined gates. Reversible logic owns its applications in various fields which include low power VLSI. In this paper multiplexer is implemented using QCA, SAM and QCA & SAM gate. Also demultiplexer is implemented using two new reversible logic gates RAMESH and RAMESH-1 gates. These designs are simulated and synthesized using Xilinx ISE 12.1 and Mentor Graphics tool. The result shows that the proposed designs are more efficient in terms of gate count, quantum cost and power consumption.

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Section: Resultsmentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

See 1 more Smart Citation

Novel design of multiplexer and demultiplexer using reversible logic gates

Nune¹,

R²

2018

IJET

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“…As illustrated in the layout the RQG gate is composed of only two three-input majority gates and one simple 2-input exclusive-OR (XOR) gate. In this efficient QCA layout, a simple and dense two-input exclusive-OR (XOR) design [13] is utilized for realization of the third output (Y3). In addition, for wire crossing, the single layer method using different clock zones is used [14,15].…”

Section: Proposed Designsmentioning

confidence: 99%

Design of an ultra-efficient reversible full adder-subtractor in quantum-dot cellular automata

Taherkhani

Moaiyeri

Angizi

2017

Optik

Self Cite

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By the progressive scaling of the feature size and power consumption in VLSI chips the part of energy dissipated due to information loss in irreversible computations will become a serious limitation in the near future. Quantum-dot cellular automata (QCA) is an emerging nanotechnology with extremely low energy dissipation which facilitates new computation paradigms such as reversible computing. In this paper a novel reversible full adder-subtractor circuit based on QCA is proposed. Our proposed design is implemented using only one layer and does not require any rotated cells which significantly improves the manufacturability of the design. In addition, it improves the cell count, area and total energy dissipation by almost 45% and 50% and 48%, respectively, as compared to the existing QCAbased single-layer and multilayer reversible full adders.Keywords: Quantum-dot Cellular Automata; Reversible computing; Full adder design; Single layer circuit; Energy dissipation analysis IntroductionPower consumption is indeed the main concern in recent VLSI circuits. Due to the ever-increasing demands for portable electronic systems and the disproportionate growth of the semiconductor and battery manufacturing industries, increasing the operational time between each battery charge has become very curtail. In addition, the disproportionate scaling of the size of transistors and power supply voltage has led to many shortcomings such as high leakage currents and high power density, creating hot spots in CMOS chips. As a result, different computational paradigms using emerging nanotechnologies, addressing drastically small size and low power dissipation, should be considered. Reversible computing is one these computational paradigms which is realized by setting up a one-toone mapping between the input and output states of the circuit [1][2][3]. In 1973 Bennett proved that it is possible to eliminate power dissipation in a logic circuit if the circuit includes only reversible logic gates. Moreover, in 1961 Landauer demonstrated that each bit of information loss in an irreversible computation leads to kBTln2 joules dissipation of heat energy, where kB is Boltzmann constant and T is temperature. As a result, the energy required for a binary transition at room temperature (T=300 K) is at least 0.017 eV. However, if a computation is carried out in a reversible manner, this amount of energy would not inevitably dissipated and energy consumption would be beyond the kBTln2 limit. Although the power dissipation of the current CMOS circuits is much higher than kBTln2, in the near future with ultimate scaling of feature size and power consumption based on emerging nanotechnologies, this theoretical limit may become a major restriction [3]. Utilizing reversible computing in nanotechnology and quantum computing has become a quite interesting subject in recent years. Reversible computing, as a new paradigm for reducing physical

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“…Above that specific temperature, accumulating errors inevitably occur and make the results wrong. [4] Besides, Landauer principles are demonstrated in [5] that the erasure of one bit of information in computing process dissipates at least kTln2 Joules. As stated in [6], the computing machines which perform logical functions with no single-valued inverse, require a minimal heat generation, per machine cycle, typically of the order of kT for each irreversible function.…”

Section: Introductionmentioning

confidence: 99%

A Novel robust Design of Toffoli gate in Quantum-Dot Cellular Automata

Abdollahi¹,

Tehrani²

2017

IJCA

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New practical researches on ultra-low power systems with noloss of information for preventing heat generation as reversible gates is making many progresses in a combination with nano-scale quantum-dot cellular automata technology. In this paper, two important design factors of QCA is investigated, Then a novel robust design of Toffoli reversible gate is proposed and compared its useful template for further uses in VLSI circuits to the others.

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Cost-efficient QCA reversible combinational circuits based on a new reversible gate

Cited by 28 publications

References 19 publications

Novel design of multiplexer and demultiplexer using reversible logic gates

Novel design of multiplexer and demultiplexer using reversible logic gates

Design of an ultra-efficient reversible full adder-subtractor in quantum-dot cellular automata

A Novel robust Design of Toffoli gate in Quantum-Dot Cellular Automata

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