Cost of Ownership/Yield Enhancement of High Volume Immersion Lithography Using Topcoat-Less Resists

Semiconductor equipment suppliers are asked to build tools that can operate almost continuously. Once such a reliable tool is developed, defect data collection, understanding, and reduction become increasingly important since the tool has to manufacture reliable (layers of) semiconductor devices that scarcely fail. At this stage, semiconductor equipment suppliers could benefit from the concepts of chip yield modeling, because it directly relates their defect data to the yield of semiconductor devices. We present a case study in which we estimate the yield impact of defects related to immersion photolithography scanners. Defects were separated into various classes, and the size distributions of those classes were measured. Given a circuit's critical area, forecasting of the yield for any defect class becomes straightforward, and also yield predictions can be made for future technology nodes, resulting in the optimal choice of yieldenhancing strategies.

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Improving Equipment Defectivity Specifications Through Chip Yield Modeling: A Case Study for Immersion Lithography

Boogaard

Smith

Mouraille

et al. 2013

IEEE Trans. Semicond. Manufact.

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Cost of Ownership/Yield Enhancement of High Volume Immersion Lithography Using Topcoat-Less Resists

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Improving Equipment Defectivity Specifications Through Chip Yield Modeling: A Case Study for Immersion Lithography

Improving Equipment Defectivity Specifications Through Chip Yield Modeling: A Case Study for Immersion Lithography

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