Counter Random Gradient Descent Bit-Flipping Decoder for LDPC Codes

Deng, Keyue; Cui, Hangxuan; Lin, Jun; Wang, Zhongfeng

doi:10.1109/isvlsi51109.2021.00021

Cited by 5 publications

(1 citation statement)

References 12 publications

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“…Tabu-list aided PGDBF (T-PGDBF) [8] adopted the tabu-search idea to avoid repeated flipping in the decoding process and was well-improved in [9]- [11]. The recent counter random GDBF (CRGDBF) [12] and PGDBF with Momentum (PGDBF w/M) [13] added the flipping histories to improve the performance further.…”

Section: Introductionmentioning

confidence: 99%

UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash Applications

Liu

Liao

Chang

2022

IEEE Open J. Circuits Syst.

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An error floor phenomenon, decoding performance, and throughput are three major concerns for LDPC decoders in NAND Flash applications. With a penalty method and an active iteration mechanism, we present a Unified Penalty Gradient Descent Bit Flipping (UP-GDBF) decoding algorithm, which not only possesses error-floor free property but also improves convergence speed in decoding performance. To fulfill the high-throughput requirement while maintaining reliable error correction capability, we propose an energy-based backtracking scheme to reduce 40% latency with a negligible 0.8% area overhead. Implemented in TSMC 16nm process, the proposed 4KB LDPC decoder can achieve a throughput of 19.3 Gbps with 0.120 mm 2 area to satisfy ONFI 5.0 throughput requirement. Compared to existing approaches, our decoder architecture provides superior data rate and decoding performance in both 1KB and 4KB LDPC codes.

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