Counterexample visualization and explanation for function block diagrams

Pakonen, Antti; Buzhinsky, Igor; Vyatkin, Valeriy

doi:10.1109/indin.2018.8472025

Cited by 18 publications

(51 citation statements)

References 15 publications

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“…Models of industrial systems contain dozens of variables, nested modules and complex dependencies [23]. In this case, being a mere table of values, counterexamples offer a limited help in localizing the issues, consuming time and resources for their decoding.…”

Section: B Linear Temporal Logicmentioning

confidence: 99%

“…Due to the possibility of explaining the outcome of ϕ through the assignments of its variables that is present in it [23], [24], we can decompose the process of explaining the outcome of ϕ to the one of explaining a number of individual assignments in the counterexample. Below, we focus on explaining a single assignment, called an explanation target.…”

Section: Counterexample Explanationmentioning

confidence: 99%

“…The explanation target can be represented by an input or output assignment of any block structure: an FBD, a modular block, or an atomic block. Initially, explanation targets come from applying the approach in [23], but we also allow the situation where the user selects a custom explanation target to focus on a particular part of D, thus allowing more flexibility in explanation.…”

Section: Counterexample Explanationmentioning

confidence: 99%

“…Oeritte incorporates two kinds of explanation techniques: the cause identification algorithm from [23] for LTL formulae failures and individual assignment explanation from Section IV for the diagram. The LTL formula explanation process may be initialized with button (Fig.…”

Section: Main Window Overviewmentioning

confidence: 99%

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Oeritte: User-Friendly Counterexample Explanation for Model Checking

et al. 2021

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Thorough verification is a part of the design process of instrumentation and control systems if they must comply with crucial safety requirements. Model checking can be applied to the formal model of such a system to reason about its correctness based on the specification provided. When a violation occurs, the model checking tool outputs the proof of the violation in the form of a failure trace, which represents a state sequence of system model transitions where the requirement does not hold. This sequence, however, even for modular systems, is a mere table of values. Due to the lack of any insights into the inner model processes and structures that caused a problem, the debugging process of the formal model becomes time and effort consuming. The tool presented in this paper, Oeritte, is aimed at assisting the analyst in this challenge. It implements a method for automatic visual counterexample explanation which includes reasoning both over the falsified LTL formula and over the NuSMV function block diagram of the formal model of the system. The tool is applied to an industrial-sized safety control system of a nuclear power plant.INDEX TERMS Counterexample explanation, counterexample visualization, function block diagram, NuSMV, user-friendly model checking.

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Section: B Linear Temporal Logicmentioning

confidence: 99%

Section: Counterexample Explanationmentioning

confidence: 99%

Section: Counterexample Explanationmentioning

confidence: 99%

Section: Main Window Overviewmentioning

confidence: 99%

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Oeritte: User-Friendly Counterexample Explanation for Model Checking

et al. 2021

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“…iSPIN [11], which we discussed above (Section 6), is the standard counterexample visualizer for SPIN. Pakonen et al developed a model checker for hardware logics, MODCHK [9], that has a visualizer showing step-by-step execution on a model of the hardware logic. It also emphasizes the important part of LTL in understanding the counterexample.…”

Section: Related Workmentioning

confidence: 99%

Visualization of Counterexamples of Memory Model-aware Model Checking Using SPIN

Matsumoto

Ugawa

2019

Journal of Information Processing

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In modern computer processors, the order of memory access instructions in a program (the "program order") is not necessarily the same as the order in which the instructions are reflected in memory (the "memory order"). This means that the memory order has to be taken into account when verifying concurrent programs. We previously developed a library, MMLib, that facilitates model checking of programs by enabling the memory order to be taken into account when using the SPIN model checker. The input to SPIN is a model of the program written in Promela, an imperative style modeling language. When SPIN detects an error, it generates a trace of the execution path that led to the error. To determine what caused the error, the user has to understand this counterexample. However, counterexamples of models written using MMLib are difficult to understand because include internal MMLib execution steps, and the user has to interpret the internal data structures of MMLib to understand the memory order. We have now In this paper, we developed software for visualizing counterexamples of models written using MMLib. It visualizes execution of the model step by step along the path of the counterexample. It skips visualizing the internal MMLib steps and visualizes only the execution of each step corresponding to statement in the user model. It also highlights memory access instructions that have been executed but have not yet been reflected in memory. This makes users aware of when the memory order differs from the program order.

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