Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling

Uhrig,; Maier, Stefan A.; Kuzmanov,; Ungerer,

doi:10.1109/ipdps.2006.1639471

Cited by 7 publications

(3 citation statements)

References 9 publications

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“…The achieved simulation performance speedup reported in [17], with an MJPEG benchmark was 2.75, having a theoretical maximum of 2.78. Since these results were quite appealing, we decided to design a system with an RTOS managing multiple concurrent user applications.…”

Section: The Molen Polymorphic Processormentioning

confidence: 94%

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Multithreading on reconfigurable hardware: An architectural approach

Zaykov

Kuzmanov

2012

Microprocessors and Microsystems

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Section: The Molen Polymorphic Processormentioning

confidence: 94%

“…In the original Molen design [16], multithreading was not considered, but in [17], interleaved multithreading (IMT) was addressed and a Hardware scheduler was used instead of an RTOS. The achieved simulation performance speedup reported in [17], with an MJPEG benchmark was 2.75, having a theoretical maximum of 2.78.…”

Section: The Molen Polymorphic Processormentioning

confidence: 99%

Multithreading on reconfigurable hardware: An architectural approach

Zaykov

Kuzmanov

2012

Microprocessors and Microsystems

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“…While earlier versions of Molen were strictly single threaded, with only one processor unit running at the same time, more recent extensions have enabled true multithreading and simultaneous operation of both the ISP and the hardware accelerator [46]. The basic idea of the Molen processor has also been applied to the FemtoJava core [34].…”

Section: Procedures Interceptionmentioning

confidence: 99%

Using method interception for hardware/software co-development

Faes¹,

Bertels

Campenhout

et al. 2009

Des Autom Embed Syst

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In many embedded systems, the computational power of an instruction set processor is combined with hardware accelerators. Building such combined systems implies co-design of the software that runs on the processor and the hardware that accelerates the embedded application. During the co-design process, the application is partitioned into a software part (running on the processor) and a hardware part (running on the accelerator). In order to ease the iterative process of partitioning, we introduce a novel design methodology. In our methodology, the interface between hardware and software is transparent to the software designer, and is based on dynamic method interception. Because the interface is transparent and generated automatically, the initial all-software prototype of the system can more easily be refined and partitioned. We show that method interception is inexpensive, and we demonstrate method interception in a real-life application. Using our methodology, embedded systems can be designed fast, reducing time-to-market, while still achieving a high run-time performance

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