Coverage of Meta-Stability Using Formal Verification in Asynchronous Gray Code FIFO

Shivali,; Khosla, Mamta

doi:10.1109/conit55038.2022.9848195

Cited by 3 publications

(3 citation statements)

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“…In the synchronous module of read pointer and write pointer, a two-level register is used [7]. When the first level register is out of metastable state, the second level register can be used as the clock delay of output data.…”

Section: Two Level Register Designmentioning

confidence: 99%

Design and optimization of asynchronous FIFO based on Verilog HDL

Cheng

2023

Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022)

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SoC system is a new chip design scheme, which can integrate a large number of functions in the same chip, so it has high requirements for asynchronous data transmission between different modules. Asynchronous FIFO is an efficient and reliable data transmission mode, which is often used as a data matcher in SoC system. This paper, through the modular design, layer by layer construction method, designs a asynchronous FIFO, and for the common problems to optimize, makes its performance more reliable. And according to the simulation results, it can be judged that this design can effectively and reliably carry out asynchronous data transmission.

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Section: Two Level Register Designmentioning

confidence: 99%

Design and optimization of asynchronous FIFO based on Verilog HDL

Cheng

2023

Second International Conference on Statistics, Applied Mathematics, and Computing Science (CSAMCS 2022)

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“…Large-capacity synchronous FIFOs are implemented using SRAM as the FIFO memory, while largecapacity asynchronous FIFOs can still be used [4]. In this article, a large-capacity synchronous FIFO and a small-capacity asynchronous FIFO are cascaded to achieve this.…”

Section: Introductionmentioning

confidence: 99%

“…The reason for this is that asynchronous FIFOs only function to transfer data across clock domains, while synchronous FIFOs are more suitable for caching data. Therefore, combining the characteristics of these two FIFOs, this article can cascade them to obtain a high-capacity asynchronous FIFO [5].…”

Section: Introductionmentioning

confidence: 99%

A verilog design for cascading a large-capacity asynchronous FIFO with a synchronous FIFO

Liu

2023

ACE

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In modern large scale ASIC designs, multiple clock systems are often involved, which can create problems with data transfer in different clock domains. A practical solution to this problem is the use of asynchronous FIFOs (First In First Out) for buffering the transfer of data from different clock domains. A high-capacity asynchronous FIFO cascaded with a synchronous FIFO is designed based on a conventional asynchronous FIFO using the Verilog language. The input data is processed across the clock domain by the asynchronous FIFO, and the data output from the asynchronous FIFO is cached and output again by the synchronous FIFO. The module increases the FIFO depth while enabling data to be transferred across the clock domain. The simulation is completed within the Modelsim software which accordingly verifies the two main roles of the FIFO in processing data, namely the cross-clock domain and the data caching function. Simulation results show that the asynchronous FIFO data is written and read correctly and that the empty/full flag signal is correct.

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A 16-Byte Asynchronous Gray Code FIFO Memory Using Verilog HDL for Real Time Applications

Himanshu,

Charan

2024

2024 2nd International Conference on Device Intelligence, Computing and Communication Technologies (DICCT)

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Coverage of Meta-Stability Using Formal Verification in Asynchronous Gray Code FIFO

Cited by 3 publications

References 0 publications

Design and optimization of asynchronous FIFO based on Verilog HDL

Design and optimization of asynchronous FIFO based on Verilog HDL

A verilog design for cascading a large-capacity asynchronous FIFO with a synchronous FIFO

A 16-Byte Asynchronous Gray Code FIFO Memory Using Verilog HDL for Real Time Applications

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