CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package

Hu, Yuping; Liang, Yu-Min; Hu, Hang; Tan, C. Y.; Shen, C. S.; Lee, Chien-Hsun; Hou, S. Y.

doi:10.1109/ectc51909.2023.00174

Cited by 23 publications

(2 citation statements)

References 4 publications

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“…The pitch of microbump connections between semiconductor chips and silicon interposers is currently around 55 μm, with some processes as low as 40 μm. 1 Microbump pitch is expected to shrink to 20 μm less to than 10 μm (single-digit) in the future and research on high-density interconnection is actively being conducted.…”

Section: Introductionmentioning

confidence: 99%

Study of submicron-resolution, high-accuracy overlay and large-field lithography for advanced packaging

Shinoda,

Shelton,

Mizutani

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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Demand for advanced graphics processing unit, field programmable gate array, and artificial intelligence (AI) chips continues to grow as many systems require more computing power for applications, such as AI processing and deep learning. To produce higher-performance chips, 2.5D silicon interposer technology has been developed and matured as a solution enabling high-speed data transmission between different chips, such as processors and dynamic random access memory. Increased I/O counts are required to enable higher bandwidth communication between semiconductor chips and silicon interposers can help realize higher-performance devices. Microbumps used to interconnect chips and interposers and redistribution layer must be scaled down to achieve high-density connections and next-generation devices also require larger interposers to support heterogeneous integration of multiple dies. We highlight the performance of the FPA-5520iV LF2-option stepper that is designed to provide the optimal stepper performance required for the next generation 2.5D interposers, including submicron resolution, high-accuracy mix-and-match overlay, and large field exposure.

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Section: Introductionmentioning

confidence: 99%

Study of submicron-resolution, high-accuracy overlay and large-field lithography for advanced packaging

Shinoda,

Shelton,

Mizutani

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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“…4 Another is using Si or glass as a carrier and form a fine wiring interposer. 5 Also in the lithography equipment, various methods have been proposed, such as direct imaging, 6 stitching, and panellevel stepper. 7 As indicated in the previous literature, larger substrate sizes have become the main trend in semiconductors in recent years.…”

Section: Introductionmentioning

confidence: 99%

Development of panel-level organic lithography equipment for advanced packaging

Sohara,

Abe,

Yamauchi

et al. 2024

J. Micro/Nanopattern. Mats. Metro.

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Background: Heterogeneous integration has been used to enhance functionality and improve operation performance by integrating separately manufactured components into system in package. To realize this high density and high performance system, continuous miniaturization is required for Cu interconnect wiring on an organic substrate.Aim: The aim is to clarify the lithography issues for 5 μm L/S Cu wiring formation in the next generation. Lithographic performances, such as resolution, depth of focus (DOF), and overlay accuracy, are evaluated on an organic substrate, and the improvement of lithographic process margin is also investigated. Here, the exposure field of stepper is wide, that is, 62500 mm 2 .Approach: The DOF is calculated and evaluated based on the negative dry film resist with thickness of 15 μm. Overlay accuracy was measured, using a multipoint alignment procedure. Result and Conclusion:First result is patterning. For realizing 5 μm L/S Cu wiring in semi-additive process, resist patterning of 3.5/6.5 or 3∕7 μm L/S is required due to seed Cu layer etching. Under two projection optics conditions (lens C: 5 μm L/S resolution and lens D: 3 μm L/S resolution), the process margin values of 3.5/6.5 and 3∕7 μm L/S were evaluated. It was found that the process margin of 3.5∕6.5 μm L/S is AE40 μm (lens C)/ AE30 μm (lens D), and the process margin of 3∕7 μm L/S is AE10 μm (lens C) AE20 μm (lens D). These process margin values are enough for 5 μm L/S Cu wiring formation. And the second result is overlay. The overlay of the lithography equipment is 1.0 μm or less for deformed substrates while maintaining productivity by simultaneous multipoint measurement.

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Flip Chip Technology

Lau

2024

Flip Chip, Hybrid Bonding, Fan-In, and Fan-Out Technology

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CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package

Cited by 23 publications

References 4 publications

Study of submicron-resolution, high-accuracy overlay and large-field lithography for advanced packaging

Study of submicron-resolution, high-accuracy overlay and large-field lithography for advanced packaging

Development of panel-level organic lithography equipment for advanced packaging

Flip Chip Technology

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