coxHE: A software-hardware co-design framework for FPGA acceleration of homomorphic computation

Mingqin, Han; Zhu, Yilan; Lou, Qian; Zhou, Zimeng; Guo, Shanqing; Ju, Lei

doi:10.23919/date54114.2022.9774559

Cited by 12 publications

(8 citation statements)

References 13 publications

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“…Furthermore, neither CPUs nor GPUs offer sufficient main memory bandwidth to cope with FHE workload's data-intensive nature. 16 23 Bootstrapping…”

Section: Related Workmentioning

confidence: 99%

“…Several studies have proposed FPGA-accelerated architecture designs for FHE [ 14 , 15 , 16 , 17 , 18 , 19 ]. Notably, Riazi et al introduced HEAX, a hardware architecture that accelerates CKKS-based HE on Intel FPGA platforms and supports low parameter sets [ 14 ].…”

Section: Introductionmentioning

confidence: 99%

“…However, the architecture faces high input/output and memory interface bandwidths, as well as costly internal memory, making it difficult to place and route multiple cores on the target FPGA platform. Han et al proposed coxHE, an FPGA acceleration framework for FHE kernels using the high-level synthesis (HLS) design flow [ 16 ]. Targeting key switching operations, coxHE examined data dependence to minimize interdependence between data, maximizing parallel computation and algorithm acceleration.…”

Section: Introductionmentioning

confidence: 99%

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Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption

Duong-Ngoc

Lee

2023

Sensors

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The increasing ubiquity of big data and cloud-based computing has led to increased concerns regarding the privacy and security of user data. In response, fully homomorphic encryption (FHE) was developed to address this issue by enabling arbitrary computation on encrypted data without decryption. However, the high computational costs of homomorphic evaluations restrict the practical application of FHE schemes. To tackle these computational and memory challenges, a variety of optimization approaches and acceleration efforts are actively being pursued. This paper introduces the KeySwitch module, a highly efficient and extensively pipelined hardware architecture designed to accelerate the costly key switching operation in homomorphic computations. Built on top of an area-efficient number-theoretic transform design, the KeySwitch module exploited the inherent parallelism of key switching operation and incorporated three main optimizations: fine-grained pipelining, on-chip resource usage, and high-throughput implementation. An evaluation on the Xilinx U250 FPGA platform demonstrated a 1.6× improvement in data throughput compared to previous work with more efficient hardware resource utilization. This work contributes to the development of advanced hardware accelerators for privacy-preserving computations and promoting the adoption of FHE in practical applications with enhanced efficiency.

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“…Furthermore, neither CPUs nor GPUs offer sufficient main memory bandwidth to cope with FHE workload's data-intensive nature. 16 23 Bootstrapping…”

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption

Duong-Ngoc

Lee

2023

Sensors

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“…There are also attempts on GPUs to achieve higher parallelism, but on single GPU, the acceleration is still inefficient and utilizing GPU cluster results in high power consumption and expense [15,16]. Using specific hardware, including FPGA and ASIC, is a promising method to further accelerate HE calculations [17,18,19,20,21,22,23,24,25,26,27,28]. In [19] and [20], circuits for accelerating HE operations are designed on single ASIC chips.…”

Section: Introductionmentioning

confidence: 99%

“…Authors in [29,30] design the accelerators for Number-Theoretic Transform (NTT)/Inverse NTT (INTT), which takes much time among low-level HE operations. [24,25,26,27,28] introduce the accelerators for high-level operations, such as key switching and ciphertext multiplication. Most structures have the pipeline design; however, the pipelines are coarse-grained and the sub-blocks are not fully-pipelined.…”

Section: Introductionmentioning

confidence: 99%

High-throughput and fully-pipelined ciphertext multiplier for homomorphic encryption

Wang,

Ikeda

2024

IEICE Electron. Express

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Homomorphic Encryption (HE) has become a promising technique to protect the data privacy in cloud computing, while its slow speed highly restricts the application. We propose a high throughput and fully pipelined implementation of ciphertext multiplier on FPGA to accelerate ciphertext multiplication, which is one of the frequently performed operations in HE applications and takes most of the calculation time. The fully pipelined architecture avoids memory access conflict and minimizes the memory usage on chip. Consequently, the logic cells, including LUTs and DSPs, are efficiently utilized for high parallelism degree and high throughput is achieved. The throughput is increased to 4.7 times compared to state-of-art FPGA designs and 1340 times of CPU performance.

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Homomorphic Encryption Library, Framework, Toolkit and Accelerator: A Review

Dhiman,

Mahato,

Chakraborty

2023

SN COMPUT. SCI.

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coxHE: A software-hardware co-design framework for FPGA acceleration of homomorphic computation

Cited by 12 publications

References 13 publications

Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption

Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption

High-throughput and fully-pipelined ciphertext multiplier for homomorphic encryption

Homomorphic Encryption Library, Framework, Toolkit and Accelerator: A Review

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