CPPC

Abstract

Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist in other memory levels. While conventional error correcting codes can protect write-back caches, it has been shown that they are expensive in terms of area and power. This paper proposes a new reliable write-back cache called Correctable Parity Protected Cache (CPPC) which adds error correction capability to a parityprotected cache. For this purpose, CPPC augments a write-back parity-protected cache with two registers: the first register stores the XOR of all data written to the cache and the second register stores the XOR of all dirty data that are removed from the cache. CPPC relies on parity to detect a fault and then on the two XOR registers to correct faults. By a novel combination of byte shifting and parity interleaving CPPC corrects both single and spatial multi-bit faults to provide a high degree of reliability. We compare CPPC with one-dimensional parity, SECDED (Single Error Correction Double Error Detection) and two-dimensional parity-protected caches. Our simulation results show that CPPC provides a high level of reliability while its overheads are less than the overheads of SECDED and two-dimensional parity.

Hi-fi playback

“…Recent research on error correction code (ECC) focuses on how to reduce the overhead, such as VS-ECC [4], CPPC [21], little-space ECC [31], etc. The work explores trade-off between reliability and area/performance/energy.…”

DeSyRe: On-demand system reliability

“…We are also studying idempotency analysis as a way to reduce updated state during task execution time. In particular we have considered decoupled codes [17,18] to protect memory arrays in one node vs. parity-protected redundant memory arrays placed on different two distinct nodes across the NoC.…”