CPU/FPGA-Based Real-Time Simulation of a Two-Terminal MMC-HVDC System

This paper presents a methodology for the design of field-programmable gate array (FPGA)-based real-time simulators (RTSs) for power electronic circuits (PECs). The programmability of the simulator results from the use of an efficient and scalable overlay architecture (OA). The proposed OA relies on a latency-insensitive design (LID) paradigm. LID consists of connecting small processing units that automatically synchronize and exchange data when appropriate. The use of such data-driven architecture aims to ease the design process while achieving a higher computational efficiency. The benefits of the proposed approach is evaluated by assessing the performance of the proposed solver in the simulation of a two-stage AC–AC power converter. The minimum achievable time-step and FPGA resource consumption for a wide range of power converter sizes is also evaluated. The proposed overlays are parametrizable in size, they are cost-effective, they provide sub-microsecond time-steps, and they offer a high computational performance with a reported peak performance of 300 GFLOPS.

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“…All internal additions are performed using the self-alignment format (SAF) [35]. Such an approach was previously adopted in [17,21,36].…”

Section: Number Formatmentioning

confidence: 99%

“…The FDP/SAF approach was previously adopted in [17,21,36] to generate dot product operators for the real-time simulation of power converters, and was shown to be computationally efficient, capable of sustaining higher clock frequencies while offering significant hardware resource savings.…”

Section: Dot Product Operatormentioning

confidence: 99%

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

2020

Self Cite

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“…The basic target of Ould‐Bachir et al is to introduce a strategy for FPGA‐based real time simulation model with the help of detailed equivalent model. Described model is verified in different case studies that are 101 level and 501 level, respectively.…”

Section: Application Areasmentioning

confidence: 99%

Recent contributions and future prospects of the modular multilevel converters: A comprehensive review

Kurtoğlu

Eroğlu

Arslan

et al. 2018

Int Trans Electr Energ Syst

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Summary The modular multilevel converters (MMCs) are frequently preferred for medium and high power energy conversion systems thanks to their modular structure and high quality output waveform. The remarkable studies related to the MMC have been carried out in recent years, which are mainly focused on its topology, control, or application. In this paper, MMC circuit topologies consisting of traditional submodule cells and new proposed configurations are introduced, and their control process, modulation techniques, and application areas are discussed in order to provide the readers the current state of the art of MMC technology. A wide part of this article is devoted to demonstrate the recent contributions arising in MMC studies. In this context, this paper not only outlines the circuit topology, control objectives, and applications of the MMC but also presents a comprehensive review, principally in terms of the latest developments of it. Ultimately, detailed proposals and new possible topics are provided to drive future expectations of MMC technology.

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“…4d2, the negative fault current also charges the voltage source v FB through T FB2 and T FB3 and gradually drops. After the fault currents are suppressed to around zero (only leakage currents exist), the system operates in the high impedance mode [25,26], as illustrated in Fig. 4e2 (none of the devices are ON).…”

Section: Switching Logics Of the Auxiliary Circuit In The Proposed Sfmentioning

confidence: 99%

Accelerated switching function model of hybrid MMCs for HVDC system simulation

Guo

2017

IET Power Electronics

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An accelerated switching function model (SFM) of the hybrid modular multilevel converter comprising both fullbridge (FB) and half-bridge (HB) submodules (SMs) in each arm is presented for HVDC system simulation, where auxiliary circuits are adopted to represent all possible current paths during normal and fault conditions. The proposed SFM can represent the negative voltage generating capability of the FB SMs and the equivalent switching functions in the blocking states of the FB and HB SMs are also introduced in the proposed model to accurately replicate the potential charging of the SM capacitors, yielding improved simulation accuracy compared to other alternatives. In addition to the faster simulation speed, the proposed model accurately reproduces the converter behaviour during various operating conditions, including normal operation, AC fault, and DC fault, etc. The proposed SFMs are assessed in MATLAB/Simulink environment using both down-and full-scale HVDC links and the simulation results confirm the validity of the proposed model in terms of model accuracy and improved simulation speed. IntroductionAs modular multilevel converters (MMCs) typically use hundreds of submodules (SMs) per arm in HVDC application, it is extremely time consuming to simulate the whole system using detailed switching models (DSMs). To reduce computation time and accelerate the simulation speed, the average model (AM) [1,2] and the accelerated SM level model [3,4] have been researched extensively to evaluate MMC performance in normal operation and during faults.In [1,5], each arm of the MMC is represented by a controllable voltage source, coupled with a series connection of a controlled current source and a DC capacitor. Such an average model provides adequate representation of the MMC behaviour seen by the external circuits under normal operation. However, the current paths during DC faults are not provided. In order to represent the response of the MMC during faults, ideal switches and a thyristor are introduced into the average value model in [6]. All the converter SM capacitors are equivalent to one DC capacitor, which is disconnected from the DC side during a DC fault. As a result, the charging of the DC capacitors in the arms by the fault current following the blocking of the MMC cannot be represented, resulting in significant errors.In [2], additional switches and diodes are added to the average model to consider the influence of the lumped DC capacitor and the unidirectional characteristics of the freewheeling arm currents during a fault. However, such model is only valid when the SM capacitance is large enough to maintain near constant SM capacitor voltages. In [7], a modified average model using six capacitors (one for each arm) and additional auxiliary circuit was developed to provide an improved representation of the MMC behaviour during various operating conditions, including AC and DC fault scenarios.To represent the detailed behaviour of individual SM, SM level models are proposed to reproduce the capacito...

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CPU/FPGA-Based Real-Time Simulation of a Two-Terminal MMC-HVDC System

Cited by 35 publications

References 16 publications

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators

Recent contributions and future prospects of the modular multilevel converters: A comprehensive review

Accelerated switching function model of hybrid MMCs for HVDC system simulation

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