Crinkle: A heuristic mapping algorithm for network on chip

Saeidi, Sara; Khademzadeh, Ahmad; Vardi, Fatemeh

doi:10.1587/elex.6.1737

Cited by 26 publications

(7 citation statements)

References 5 publications

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“…In this experiment, both randomly generated graphs and real benchmarks are evaluated. The proposed algorithm is compared against INC, 17 Nmap, 24 Castnet 31 and Crinkle 28 algorithms. We have extended the algorithms Nmap, CastNet and Crinkle to support 3D NoC.…”

Section: Experimental Results and Analysismentioning

confidence: 99%

“…Crinkle 28 is a heuristic algorithm which is based on lists of prioritized tasks. First, the priority lists are organized according to the maximum communication volume or maximum out‐degree.…”

Section: Related Work and Motivationmentioning

confidence: 99%

“…Table 1 highlights that most of the proposed works use static mapping algorithms 13,14,23,24,27,28,31 . Some of them 13,14,23 are based on GA, BB, PSO and SA .…”

Section: Related Work and Motivationmentioning

confidence: 99%

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A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC

Gaffour

Benhaoua

Benyamina

et al. 2021

Concurrency and Computation

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Summary Three‐dimensional Network‐on‐Chip (3D NoC) is a promising solution for solving 2D NoC problems while optimizing the system's performance. Mapping applications in 3D NoC is a crucial step as it has a significant impact on overall system performance. Moreover, multi‐task supported processing elements (PEs) are needed to run multiple applications and provide more scalability. Most of the existing 3D mapping approaches consider only the single‐task platform. In this paper, we propose an efficient multi‐task mapping algorithm targeting regular 3D NoC that allows an incremental mapping and parallel execution of many applications onto different partitions on the 3D NoC. The proposed mapping algorithm is composed of three main steps aiming to reduce the communications overhead, exploiting the benefits of vertical links and improving the performances. The algorithm has been evaluated with various random and realistic benchmarks and compared with existing mapping algorithms for 3D NoC. The experimental results demonstrate that the proposed mapping strategy achieves significant performance in terms of communication cost, energy consumption and execution time.

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Section: Experimental Results and Analysismentioning

confidence: 99%

Section: Related Work and Motivationmentioning

confidence: 99%

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A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC

Gaffour

Benhaoua

Benyamina

et al. 2021

Concurrency and Computation

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“…A similar approach has been discussed in [89]. In [90], priority lists are created based on the communication bandwidth and degree of interconnection between nodes before mapping. Tasks are then mapped in a zigzag manner starting from one corner and end on another corner of the mesh-based NoC.…”

Section: • Constructive Heuristic With Iterative Improvementmentioning

confidence: 99%

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

et al. 2020

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Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the highperformance constraints of composite embedded applications is on the rise. This leads to the realization of efficient mapping approaches for such complex applications. The significance of efficient application mapping approaches has increased ever since the embedded applications have become more complex and performance-oriented. This paper presents the detailed comparative analysis and categorization of application mapping approaches with current trends in NoC design implementation. These approaches target to improve the performance of the whole system by optimizing communication cost, energy, power consumption, and latency. Apart from the categorization of the discussed approaches, comparison of communication cost, power, energy, and latency of the NoC system carried out on real applications like VOPD and MPEG4. Moreover, the best technique identified in each category based on the evaluation of performance results. INDEX TERMS Network-on-Chip, application mapping, NoC design, VOPD, System-on-Chip. I. INTRODUCTION System-on-Chip (SoC) is an archetype for the design and implementation of on-chip circuits that can support multiple systems on a single chip. The ever-rising number of processing cores on a single chip has made the efficiency of onchip designs as one of the major aspects in evaluating the average performance of embedded SoC. To fulfill the performance needs and to provide flexibility in the designs the field of Network on Chip (NoC) has emerged that separates the communication from the computation. Many surveys [1]-[7] are published in general and textbooks are also available on the topic [8]-[10]. There is still a need to solve more advanced research problems in NoC. Application mapping on NoC architecture has a prominent place among all the research problems which can be arbitrated from the published The associate editor coordinating the review of this manuscript and approving it for publication was Eyuphan Bulut. papers and current trends. This survey assumes a textbooklevel acquaintance of NoC terminology. The aim is to provide a comprehensive overview of all the aspects of application mapping (task graph generation, scheduling, optimization techniques, simulation setup, and performance evaluation metrics). The organization of this survey is as follows; first, we provide the reader the need and overview of application mapping in NoC presented in Section I. A detailed review and calcification of application mapping techniques in NoCs are discussed in Section II. The current and latest trends in application mapping are summarized in Section III. In Section IV performance comparison and the points that can create the difference between these techniques are highlighted. Finally, Section VI concludes this paper. A. MOTIVATION AND SCOPE Mostly synthetic traffic patterns are used to imitate the functionalities of rea...

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“…In this section, we refer to the following weighted directed graphs to formulate this problem [10]. Definition 1: An Application Characterization Graph (APCG), is a directed weighted graph G(C, A), where each vertex c i ∈ C denotes an IP core, the directed arc a ij ∈ A denotes a communication trace from the IP core c i to the IP core c j , and the weight of each edge w ij indicates the communication volume on edge a ij .…”

Section: Mapping Modelmentioning

confidence: 99%

WOAGA: A new metaheuristic mapping algorithm for large-scale mesh-based NoC

Wang

Sun

et al. 2018

IEICE Electron. Express

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The mapping of IP cores to the topology is one of the most important steps for NoC (Network-on-Chip) design. Metaheuristic algorithms (MAs) are widely employed since the mapping is an NP-hard problem. Most mapping algorithms only consider small-scale NoC and ignore stability. In this letter, a stable metaheuristic algorithm called WOAGA, based on Whale Optimization Algorithm (WOA) and Genetic Algorithm (GA), is proposed for large-scale NoC mapping to achieve the low-energy consumption and stability. In the proposed algorithm, irregular crossover and mutation operations are integrated into the modified WOA. A perturbation is utilized to jump out of local optima effectively. Simulation results show that the proposed algorithm is more stable and achieve better solution with energy consumption reduced significantly.

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Crinkle: A heuristic mapping algorithm for network on chip

Cited by 26 publications

References 5 publications

A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC

A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC

Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

WOAGA: A new metaheuristic mapping algorithm for large-scale mesh-based NoC

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