Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

Abstract

This work presents an efficient hybrid simulation approach, developed for accurate characterization of single-event transients (SETs) in combinational logic. Using this approach, we show that charges as small as 3.5fC can introduce transients in commercial 90nm CMOS technology, hence increasing the likelihood of SETinduced soft errors. SET pulse-widths as large as 942ps are predicted at an LET (Linear Energy Transfer) of 60MeV-cm 2 /mg. Process-corner variations are shown to modulate SET pulse-widths by up-to 75%. The results suggest that selection of mitigation techniques for SET radiation-hardened circuits cannot exclusively rely on baseline process analyses, as they might grossly underestimate the true SET risk to the design.

SET Pulse Characterization and SER Estimation in Combinational Logic with Placement and Multiple Transient Faults Considerations

“…Once a transient glitch is generated by a particle hit, it propagates through the following gates and may reach a memory element, if its width is sufficient enough. As mentioned, SET propagation is determined by the strength of the particle and, as a result, by the glitch amplitude and width, and the gates that belong to the corresponding propagation cone, since each one of them has different nodal capacitance affected by parasitic delay and fan-out [36].…”