Critical Dimension Control for 32 nm Node Random Contact Hole Array Using Resist Reflow Process

Park, Joon-Min; Kang, Young-Min; Hong, Jung Hee; Oh, Hye−Keun

doi:10.1143/jjap.47.1158

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…Patterndependent RRP using an optical proximity correction (OPC) mask is attempted to improve CH width uniformity by including serif on the mask. 3) Thus, we were able to obtain uniform CH CD after RRP with an OPCed pattern (Fig. 3 and Table II).…”

Section: Various Ch Simulation Resultsmentioning

confidence: 68%

Resist Reflow Process for 32 nm Node Arbitrary Pattern

Park

2009

jjap

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In order to decrease the size of contact holes, which is usually much larger than other patterns, the resist reflow process (RRP) has been widely used. Various types, shapes, and pitches of contact hole arrays are generated by RRP, but the use of RRP was limited to only contact hole patterns. The use of the same RRP method is expanded to 32 nm node arbitrary and complex patterns including dense line and space patterns. There might be simple one-dimensional patterns, but two-dimensional proximity conflict patterns are difficult to generate in general. In particular, the data split with proximity correction requires much attention for double patterning. 32 nm node arbitrary patterns could be generated using RRP without complex data splits when high-index fluid immersion lithography [numerical aperture (NA) 1.55] is used.

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Section: Various Ch Simulation Resultsmentioning

confidence: 68%

Resist Reflow Process for 32 nm Node Arbitrary Pattern

Park

2009

jjap

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“…RRP can reduce the LER of the pattern as well as make smaller contact holes. [18][19][20][21] According to the 2008 ITRS roadmap (Table I), 22) LWR must be close to 1.3 nm in 3 for a 22 nm half pitch (hp).…”

Section: Introductionmentioning

confidence: 99%

Line Edge Roughness Reduction Using Resist Reflow Process for 22 nm Node Extreme Ultraviolet Lithography

Cho

Kim

You

et al. 2010

Jpn. J. Appl. Phys.

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Extreme ultraviolet lithography (EUVL) has been developed and studied for a sub-22 nm semiconductor device. It is difficult to obtain a smooth sub-22 nm pattern because line edge roughness (LER) and linewidth roughness (LWR) cannot be controlled well. According to the 2008 ITRS roadmap, LER has to be below 1.3 nm to achieve a 22 nm node for EUVL. In our previous work, the resist reflow process (RRP), in which the resist is baked above the glass transition temperature (T g ), was very helpful for reducing LER and LWR for EUVL. LER and LWR could be decreased from 6 to 1 nm. As RRP time progresses, however, the critical dimension could become wider because the developed resist can flow more easily when the temperature is above T g . Therefore, another method is suggested to solve this problem. The developed resist, which is intentionally designed with a 1 : 3 line and space (L/S) (11 : 33 nm) pattern, is baked above T g . As a result, LER and LWR can be smoothed by RRP and we could achieve a 22 nm 1 : 1 L/S pattern with a small LER. #

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Critical Dimension Control for 32 nm Node Random Contact Hole Array Using Resist Reflow Process

Cited by 2 publications

References 3 publications

Resist Reflow Process for 32 nm Node Arbitrary Pattern

Resist Reflow Process for 32 nm Node Arbitrary Pattern

Line Edge Roughness Reduction Using Resist Reflow Process for 22 nm Node Extreme Ultraviolet Lithography

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