Critical dimension control of a plasma etch process by integrating feedforward and feedback run-to-run control

Chemali, Chadi El; Freudenberg, J.S.; Hankinson, Matt; Collison, Wenli; Ni, Tom

doi:10.1116/1.1615983

Cited by 12 publications

(4 citation statements)

References 2 publications

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“…Since each local CD is directly controlled by the local PEB temperature in steady state, the CDs at certain zone offsets combination can be expressed as (4) where is the controller offset for zone and is the number of sites where the CD is measured on each wafer. The CD for site , denoted , is a function of the seven zone offsets of the bake plate since each zone offset affects PEB temperature globally across the plate.…”

Section: Cd-to-offset Modelmentioning

confidence: 99%

Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment

Zhang

Poolla

Spanos

2007

IEEE Trans. Semicond. Manufact.

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Across-wafer gate critical dimension (CD) uniformity impacts chip-to-chip performance variation vis-à-vis speed and power. Performance specification for across-wafer CD uniformity has become increasingly stringent as linewidth decreases to 90 nm and below. This paper presents a novel approach to improve across-wafer gate CD uniformity through the lithography and etch process sequence. The proposed approach is to compensate for upstream and downstream systematic CD variation components in the litho-etch process sequence by optimizing across-wafer post exposure bake (PEB) temperature profiles. More precisely, we first construct a temperature-to-offset model that relates the PEB temperature profiles to the setpoint offsets of multi-zone PEB plates. A second model relating across-wafer CD to setpoint offsets of PEB plates is then identified from CD scanning electron microscope measurements. Post-develop and post-etch CD uniformity enhancement methodologies are then proposed based on the CD-to-offset model and temperature-to-offset models. The temperature-to-offset model is determined to be more appropriate for use in CD uniformity control due to its superior fidelity and portability as compared with the CD-to-offset model. We demonstrate that about 1-nm reduction in standard deviation of post-etch CD variation was achieved in the verification experiment, which validated the efficacy of proposed CD uniformity control approach.Index Terms-Constrained quadratic programming, critical dimension (CD), critical dimension uniformity (CDU), multiobjective optimization, multizone PEB bake plate, plasma etch bias signature, postexposure bake (PEB), process control, process modeling.

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Section: Cd-to-offset Modelmentioning

confidence: 99%

Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment

Zhang

Poolla

Spanos

2007

IEEE Trans. Semicond. Manufact.

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“…The variation in different chambers is caused from the behavior of different etching equipments, which means the bias is in the chamber. However, most of the existing studies for advanced process control (APC) have investigated the CD variation reduction regarding the within-wafer, W2W and L2L CD control (El Chemali et al 2003;Williams et al 2005;Zhang, Poolla, and Spanos 2008;Parkinson et al 2010). Little research addresses the CD control between lots etched in different chambers to compensate the bias in etching process.…”

Section: Introductionmentioning

confidence: 97%

Manufacturing intelligence for determining machine subgroups to enhance yield in semiconductor manufacturning

Chien

Chen

Hsü

et al. 2011

Proceedings of the 2011 Winter Simulation Conference (WSC)

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Linewidth control is a critical issue for yield enhancement in semiconductor manufacturing. Most of the existing techniques such as run-to-run control have been developed to control the critical dimension (CD) in photolithography and etching process. However, few studies have addressed the tool behavior that would also affect the result of CD in etching process and the etch bias that is the CD difference between photolithograph and etching process. This study aims to propose a manufacturing intelligence (MI) approach to develop dispatching rules for etching tool in order to reduce the variation of critical dimension measured after etching process and determine the machine subgroups for compensating the etching bias. An empirical study was conducted to estimate the validity of proposed approach and the results showed practical viability of this approach. INTRODUCTIONWith the shrinking feature size of integrated circuits (ICs) in advanced technology, the tolerance of critical dimension (CD) becomes tight and slight. Photolithography and etching are two main process for determining CD in semiconductor manufacturing. The CD is the minimum width of patterned line or the distance between two pattern lines. In particular, the measurement of CD after exposure and development in photolithography process is developed critical dimension (DCD) and the CD measured after etching process called etched critical dimension (ECD), which represents the final linewidth for each layer. The ECD directly affects semiconductor device performance. In order to assure product quality and process yield, ECD must be controlled within the tolerance precisely. ECD variation may occur within a wafer, from wafer-to-wafer (W2W), from lot-to-lot (L2L) and between lots etched in different chambers. The CD variation occurred within a wafer is usually represented by the uniformity. It is generally a consequence of reactor design and determined by factors such as gas flow pattern, chamber symmetry and plasma source configuration. Wafer-to-wafer and lot-to-lot CD variation may occur because of poor repeatability at equipment, process and photolithography on incoming 1893 978-1-4577-2109-0/11/$26.00 ©2011 IEEE

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“…A control model has been proposed in which the gate bias power for etching is optimized by using scanning electron microscopy (SEM) to measure the width of the photoresist pattern prior to etching and using feedforward to the controller. [8][9][10][11] However, this control model did not realize real-time process control based on highly accurate information about the radicals, which directly determine the process characteristics.…”

Section: Introductionmentioning

confidence: 99%

An Autonomously Controllable Plasma Etching System Based on Radical Monitoring

Takahashi¹,

Kawauchi²,

Takashima³

et al. 2012

Jpn. J. Appl. Phys.

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The optimum conditions for a plasma etching device are generally determined from the results of etching a sample while varying an external parameter (e.g., gas mass flow, gas mixing ratio, process chamber pressure, or plasma source power). However, to realize controlled plasma etching with few fluctuations on a subnanometer scale, it is essential to develop a system that is controlled in real-time based on internal plasma parameters (e.g., densities and energies of radicals and ions), which directly determine process characteristics, rather than external plasma parameters. We have developed an autonomously controlled plasma etching system that performs integrated monitoring of radicals in the gas phase and on the surface of films. The etching rate of organic materials could be autonomously controlled based on hydrogen and nitrogen radical densities obtained in real-time.

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Critical dimension control of a plasma etch process by integrating feedforward and feedback run-to-run control

Cited by 12 publications

References 2 publications

Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment

Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment

Manufacturing intelligence for determining machine subgroups to enhance yield in semiconductor manufacturning

An Autonomously Controllable Plasma Etching System Based on Radical Monitoring

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