Critical processing issues for micromachined sacrificial layer etching and sealing

Berney, Helen; Kemna, A.; Hill, M.T.; Hynes, E.; O'Neill, M.; Lane, W.A.

doi:10.1016/s0924-4247(98)00373-2

Cited by 9 publications

(11 citation statements)

References 15 publications

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“…The cavity gap was reduced from 200 nm to 60 nm after nitride deposition. This phenomenon has been already observed by Berney et al [12]. LPCVD 12 silicon nitride is not a suitable candidate for the sealing of cavities, due to its poor value of the sticking coefficient [13].…”

Section: Vacuum Sealing Of Cmutmentioning

confidence: 71%

Optimization of the fabrication of sealed capacitive transducers using surface micromachining

Belgacem

Alquier²,

Muralt

et al. 2003

J. Micromech. Microeng.

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Processing issues for the fabrication of capacitive micromachined ultrasonic transducer (cMUT) arrays have been studied using surface micromachining. This work focuses on the critical steps of process fabrication such as membrane formation, sacrificial layer properties and vacuum sealing performance of cavity. We describe a four-mask process for the realization of sealed cMUT. We demonstrate that the use of a sacrificial layer with a columnar structure gives a fast etching rate (29 nm s −1 ) in a buffered hydrofluoric acid solution. The mechanical stress of LPCVD silicon nitride (SiN x ), used as membrane, was evaluated. We compared the vacuum sealing performance of different materials in order to find the best material in terms of lateral deposition inside the cavity. Functional transducers have been obtained. We proposed an electrical test in order to evaluate the vacuum sealing of the cavity based on the collapse voltage determination. Laser interference measurements were used to characterize the dynamic displacement of the membrane.

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Section: Vacuum Sealing Of Cmutmentioning

confidence: 71%

Optimization of the fabrication of sealed capacitive transducers using surface micromachining

Belgacem

Alquier²,

Muralt

et al. 2003

J. Micromech. Microeng.

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“…The pressure sensitive field effect transistor (FET) developed at the National Microelectronics Research Centre (NMRC) [9][10][11] was manufactured by creating a sealed evacuated cavity between a polysilicon sensing diaphragm (FET gate) and a silicon substrate which contained source and drain regions. The sealed cavity forms part of the FET gate dielectric.…”

Section: Sensor Descriptionmentioning

confidence: 99%

“…Pressure applied to the polysilicon diaphragm causes it to deflect thereby changing the effective dielectric thickness. This dielectric thickness variation changes the FET output current creating a pressure to current transducer [10,12]. A schematic of the sensor gate, source and drain is shown in figure 2(a) and a scanning electron microscopy image of a finished pressure membrane is shown in figure 2(b).…”

Section: Sensor Descriptionmentioning

confidence: 99%

Determination of the effect of processing steps on the CMOS compatibility of a surface micromachined pressure sensor

Berney¹,

Hill²,

Cotter³

et al. 2001

J. Micromech. Microeng.

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A surface micromachining process for the fabrication of a pressure sensitive field effect transistor (FET), compatible with complementary metal oxide semiconductor (CMOS) processing, has been established in which residual membrane stress can be tuned without changing the underlying CMOS operation. The residual membrane stress must be controlled at a low tensile value for optimum operation of the pressure FET. Controlling this residual stress involves the development of suitable processing conditions, and the effect of alteration from standard CMOS processing on the underlying circuitry must be evaluated. The effects of different processing conditions for a surface micromachined polysilicon pressure sensing membrane on the CMOS characteristics are presented. Variations in the polysilicon sensor layer deposition and implant conditions in the surface micromachining process and back-end CMOS interlayer dielectric reflow were examined as these strongly influence the residual stress in the membrane. The electrical characteristics for devices that had only CMOS processing did not vary significantly from the electrical characteristics of devices that had the pressure sensor surface micromachining layer processing.

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“…1). This is typically done by chemical vapor deposition (CVD), sputtering or E-beam evaporation of a sealing layer [11], [13], [20], [22]. In some cases, oxide layers grown by thermal oxidation of silicon can be employed [13], [22], [23].…”

mentioning

confidence: 99%

“…As shown in Fig. 1c-d, these may introduce mechanical stress (deformation) [22], increase the topography [19], and reduce the transparency of the channel.…”

mentioning

confidence: 99%

Stiction-Induced Sealing of Surface Micromachined Channels

Morana

Poelma

Fiorentino

et al. 2014

J. Microelectromech. Syst.

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We established a technique to achieve low temperature hermetic sealing of surface micromachined channels by exploiting stiction. Using a wing-shaped structural layer, microchannels automatically seal during the drying step that follows the sacrificial etch. This avoids the need of plugging layers to close the apertures of the sacrificial etch. To demonstrate the technique, we designed a surface micromachined channel with a structural layer made of polycrystalline silicon carbide (poly-SiC). This layer integrates an array of anchored pillars to achieve long and wide microchannels (5.4 mm × 0.43 mm × 0.001 mm). To dimension the sealing-wing, we estimate the minimum adhesion energy between the poly-SiC and silicon. This is done by analytical modeling and experimental characterization of test structures in the shape of centrally-supported circular plates. The bending and adhesion of the sealing-wing is followed in situ by optical microscopy. The closed microchannels are annealed at 100°C. Some structures are exposed to thermal stress at 760°C. The results are inspected by white light interferometry, scanning electron microscopy, and helium leak testing. Microchannels result hermetically sealed showing leak rates below the detection limit (4 × 10 −9 Pa · m 3 /s). The seal is effective to at least 600 kPa.[2013-0122]

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Critical processing issues for micromachined sacrificial layer etching and sealing

Cited by 9 publications

References 15 publications

Optimization of the fabrication of sealed capacitive transducers using surface micromachining

Optimization of the fabrication of sealed capacitive transducers using surface micromachining

Determination of the effect of processing steps on the CMOS compatibility of a surface micromachined pressure sensor

Stiction-Induced Sealing of Surface Micromachined Channels

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