Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded Systems

Muttillo, Vittoriano; Valente, G.; Pomante, Luigi

doi:10.1145/3183767.3183782

Cited by 6 publications

(6 citation statements)

References 19 publications

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“…The considered use case, or the Time-to-completion (TTC) timing constraint that drives the DSE steps, and the genetic algorithm parameters are described in [13]. From this example it is clear that elitism is one of the most important feature needed by a Genetic algorithms, but it introduces timing overheads (as shown in the last figure in [14]), and a correct way to implement this functionality is one of the main problem in this field.…”

Section: Resultsmentioning

confidence: 99%

“…From this example it is clear that elitism is one of the most important feature needed by a Genetic algorithms, but it introduces timing overheads (as shown in the last figure in [14]), and a correct way to implement this functionality is one of the main problem in this field. The next paragraph describe the results obtained using the proposed PGA approach, while the reference use case and the GA configurations have been extracted from [13]. The PGA has been tested on a PC with Intel Core i5-2430M dual-core (2.40 GHz), 4GB di RAM and Linux Ubuntu distribution.…”

Section: Resultsmentioning

confidence: 99%

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An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems

Muttillo

Giammatteo

Fiorilli

et al. 2020

Proceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures / 9th W

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Heterogeneous multiprocessor platforms are becoming widespread in the embedded system domain, mainly for the opportunity to improve timing performance and to minimize energy/power consumption and costs. Therefore, when using such platforms, it is important to adopt a Design Space Exploration (DSE) strategy that considers compromises among different objectives. Existing DSE approaches are generally based on evolutionary algorithms to solve Multi-Objective Optimization Problems (MOOPs) by minimizing a linear combination of weighted cost functions (i.e., Weighted Sum Method, WSM). In this way, the main issues are related to reduce timing execution while trying to improve the evolutionary algorithm performance, introducing strategies that attempt to bring better solutions. Code parallelization is one of the most used approaches in this field, but no standard methods have been released since different aspects could affect the performance. This approach leads to exploit parallel and distributed processing elements in order to implement evolutionary algorithms. In the latter case, if we consider genetic algorithms, it is possible to talk about Parallel Genetic Algorithms (PGA). Considering this context, this paper focuses on DSE for heterogeneous multi-processor embedded systems and introduces an improvement that reduces execution time using parallel programming languages (i.e., OpenMP) inside the main genetic algorithm approach, while trying to lead to better partitioning solutions. The descriptions of the adopted DSE activities and the OpenMP implementation, validated by means of a case study, represent the core of the paper. CCS CONCEPTS • Computer systems organization → Embedded systems; Embedded hardware;

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems

Muttillo

Giammatteo

Fiorilli

et al. 2020

Proceedings of the 11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures / 9th W

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“…Thex vector represents application processes and values in the decision variable space are BB instances, so the solution space is bounded by the total number of BBs. The cost functions depends on different metrics evaluated/estimated during the co-design flow [2,14]. Then, a multi-objective genetic algorithm is used to individuate an approximation of the ρF * in a single run, where, starting from the phenotype space, the solution has been encoded considering application processes and BBs.…”

Section: Reference Design Space Exploration Approachmentioning

confidence: 99%

Tuning DSE for Heterogeneous Multi-Processor Embedded Systems by means of a Self-Equalized Weighted Sum Method

Muttillo

Fiorilli

Mascio

2019

Proceedings of the 10th and 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures

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Heterogeneous multi-processor platforms are becoming widely diffused in the embedded system domain, mainly because of the opportunity to improve timing performance and, at the same time, to minimize energy/power consumption and costs. In using such kind of platforms, to be able to consider the trade-offs among different goals, a Design Space Exploration (DSE) is generally adopted. For this, existing DSE approaches typically rely on evolutionary algorithms to solve Multi-Objective Optimization Problems (MOOP) by minimizing a linear combination of weighted objective functions (i.e., Weighted Sum Method, WSM). The problem is then shifted towards the identification of weights able to represent desired tradeoffs. In such a context, this paper focuses on DSE for heterogeneous multi-processor embedded systems and introduces an approach that, while still driven by a "decision maker", is able to self-tune weights to equalize objective functions contribution. In particular, this work presents a self-equalized WSM integrated into a genetic algorithm used to identify sub-optimal implementation alternatives in the context of an Electronic System Level HW/SW Co-Design flow. CCS CONCEPTS • Computer systems organization → Embedded systems; Embedded hardware.

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“…Anyway, full virtualization is generally not satisfactory for embedded systems (especially if exists real-time constraints), indeed the required overhead may be impactful on the temporal constraints of the application. The usage of Hypervisors [11] in these situations permits to run ate the same time several operating systems upon a platform in sharing with low overhead, but still maintaining the isolation of time and space [12].…”

Section: Isolation In Mixed-criticality Systemsmentioning

confidence: 99%

A Lightweight, Hardware-Based Support for Isolation in Mixed-Criticality Network-on-Chip Architectures

Valente¹,

Giammatteo²,

Muttillo³

et al. 2019

Adv. sci. technol. eng. syst. j.

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Spatial and temporal isolation is a crucial issue in embedded systems executing multiple tasks with several levels of criticality. This is considerably significant in the context of multi-processor (or multi-core) embedded systems running multiple mixed-criticality applications in parallel. This work deals with the issue of isolation of different application classes on Network on Chip (NoC) architectures and proposes a lightweight hardware mechanism able to support mixed-criticality requirements and specifically designed to be introduced into existing network interfaces. This mechanism supports the execution of different and contemporary applications with several criticality levels by supervising the messages exchange among network nodes, with the introduction of limited hardware and software overhead on the monitored network. The proposed solution is described and evaluated by means of logical simulations and an implementation on reconfigurable logic, using a reference NoC architecture with mesh topology. Scalability of the proposed approach is also discussed and evaluated by means of network simulations. Results show an area occupation less than 1% in a 3x3 mesh NoC, and a good scalability of the proposed mechanism in an 8x8 mesh network, indicating it as a valid lightweight solution able to enforce isolation in NoCs.

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Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded Systems

Cited by 6 publications

References 19 publications

An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems

An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems

Tuning DSE for Heterogeneous Multi-Processor Embedded Systems by means of a Self-Equalized Weighted Sum Method

A Lightweight, Hardware-Based Support for Isolation in Mixed-Criticality Network-on-Chip Architectures

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