Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processor

Laurent, Johan; Beroulle, Vincent; Deleuze, Christophe; Pebay-Peyroula, Florian; Papadimitriou, Athanasios

doi:10.1016/j.micpro.2019.102862

Cited by 13 publications

(6 citation statements)

References 3 publications

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“…Laurent et al [90] explore fault injection at the microarchitectural layer and propose a cross-layer approach. This approach cojoins software and hardware characteristics to improve countermeasures with reasonable overhead.…”

Section: A Securitymentioning

confidence: 99%

A Survey of the RISC-V Architecture Software Support

et al. 2022

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RISC-V is a novel open instruction set architecture that supports multiple platforms while maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has been increasing in the last years, given that popular tool-chains and operating systems already have support for RISC-V. However, although many works have been exploring the RISC-V software ecosystem, no work that raised the current state of software support for RISC-V is available. In this context, this survey reviews the contributions introduced in the last years to understand the RISC-V's software ecosystem and its usage in both academic and industrial environments. We classified and evaluated the works into four main categories: fields of application, RISC-V implementations, software architecture, and deployment features. The primary goal of this research is to provide the community with a comprehensive overview of the current state of the art of RISC-V software support and identify and highlight the main contributions of recent works.

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Section: A Securitymentioning

confidence: 99%

A Survey of the RISC-V Architecture Software Support

et al. 2022

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“…Finally, in [19], Laurent et al, suggested that fault simulations using typical software fault models (such as instruction-skip and test-inversion) are no longer enough to characterize the observed faulty behaviours, in particular when targeting complex microprocessors that have a large number of internal elements, i.e. registers and combinational logic.…”

Section: Institute Of Engineering Univ Grenoble Alpesmentioning

confidence: 99%

Cross-layer inference methodology for microarchitecture-aware fault models

Alshaer¹,

Colombier²,

Deleuze³

et al. 2022

Microelectronics Reliability

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“…But they do not consider combinedfault attacks and they do not improve the selection of fault injection settings. Finally, Laurent et al [10] use Register-Transfer Level (RTL) fault models, that closely match the processor faulty behaviours, to assist in the fault analysis at source code level by detecting previously unnoticed vulnerabilities. Nevertheless, they do not optimize the selection of fault injection settings and do not consider combined fault attacks.…”

Section: E Related Workmentioning

confidence: 99%

An End-to-End Approach for Multi-Fault Attack Vulnerability Assessment

Werner

Maingault

Potet

2020

2020 Workshop on Fault Detection and Tolerance in Cryptography (FDTC)

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Although multi-fault attacks are extremely powerful in defeating sophisticated hardware and software defences, detecting and exploiting such attacks remains a difficult problem, especially without any prior knowledge of the target. Our main contribution is an end-to-end approach for multi-fault attack vulnerability assessment We take advantage of target specific fault models rather than generic fault models to achieve complex multi-fault attacks that can lead to critical vulnerabilities. Target specific fault models are generated thanks to fault models inference process, based on a fault injections simulation and a characterization, in order to elaborate powerful multifault attacks based on different fault models. Combining fault models opens up new possible attack paths and adds flexibility to design fault attacks that adapt to countermeasures. Hence, the direct consequence of the increasing complexity of fault attacks question the effectiveness of software countermeasures based on generic fault models for sensitive applications.

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Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processor

Cited by 13 publications

References 3 publications

A Survey of the RISC-V Architecture Software Support

A Survey of the RISC-V Architecture Software Support

Cross-layer inference methodology for microarchitecture-aware fault models

An End-to-End Approach for Multi-Fault Attack Vulnerability Assessment

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