Cross-layer Floorplan Optimization For Silicon Photonic NoCs In Many-core Systems

Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System

“…Architecture and layout adaptation to the requirements of a 3-D-stacked architecture is another related research field [19], [24], [31]. The optical layer routing problem is formulated and solved in [23] and [24], so to minimize the optical loss in the ONoC given a fixed netlist. Other frameworks extend the scope from routing to the complete placement and routing process, either viewing these steps sequentially [18], or implementing some form of crosslayer optimization [22], [26].…”

“…Some frameworks augment P&R algorithms with thermal profile awareness [22]. A more comprehensive approach in [23] considers even scheduling policy, thermal tuning, and heterogeneity in chip power profiles. The above works suffer from one or more of the following issues.…”

“…1) They focus on optical routing geometries, thus failing to capture the topologic level [20], [21]. 2) They tackle the P&R challenge mainly for physically distributed [27] or ring-equivalent structures [23], while centralized topologies are trivially placed in the middle of the die [29]. Therefore, the problem of unfolding a topology into physical partitions has never been thoroughly addressed before.…”

“…For each communication that needs to be implemented in the ring (loop in line 5 of the pseudocode), the algorithm first tries to set the connection on the minimal path between the two nodes reusing a wavelength already present in the design (lines 8-16). If that is not possible because some of the required ring sections are not free in any waveguide with any of the existing wavelengths, a new wavelength will be added to set the communication (lines [19][20][21][22][23][24][25]. If the maximum number of wavelengths had already been reached, then the algorithm will try to set the communication on the nonminimal path, going around the ring in the other direction (lines 28-36).…”

Layout optimization methodology for ring-based on-chip optical network

“…Other switching-based networks are bufferless during the transmission from an input port to the output port, and the transmission can be regarded as one hop [16,17,18,19]. In addition to the network topology, the layout optimization methodologies are proposed to eliminate the gap between logic design and chip layout [20,21,22,23].…”