Cross-Layer Modeling and Simulation of Circuit Reliability

Cao, Yu; Velamala, Jyothi; Sutaria, Ketul B.; Chen, Mike Shuo-Wei; Ahlbin, J. R.; Esqueda, Ivan Sanchez; Bajura, Michael; Fritze, M.

doi:10.1109/tcad.2013.2289874

Cited by 51 publications

(12 citation statements)

References 41 publications

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“…On the one hand, the In 0.53 Ga 0.47 As FinFET delivers a larger on-current than the Si device but for the price of increase in leakage current when compared to than observed in the Si FinFET. Therefore, the (I ON /I OFF ) ratio, close to 6x10 4 , is similar for the both devices. This variability study uses three different simulation tools in a hierarchical workflow from a quantum-transport through a semi-classical to a classical technique.…”

Section: Finfet Modellingmentioning

confidence: 62%

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Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

Seoane

Indalecio

Aldegunde

et al. 2016

IEEE Trans. Electron Devices

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Copies of full items can be used for personal research or study, educational, or not-for profit purposes without prior permission or charge. Provided that the authors, title and full bibliographic details are credited, a hyperlink and/or URL is given for the original metadata page and the content is not changed in any way.Publisher's statement: "© 2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting /republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works." A note on versions:The version presented here may differ from the published version or, version of record, if you wish to cite this item you are advised to consult the publisher's version. Please see the 'permanent WRAP url' above for details on accessing the published version and note that access may require a subscription. Abstract-The fin edge roughness (FER) and the TiN metal grain work-function (MGW) induced variability affecting off and on device characteristics is studied and compared between a 10.4 nm gate length In 0.53 Ga 0.47 As FinFET and a 10.7 nm gate length Si FinFET. We have analysed the impact of variability by assessing five figures of merit (V T , SS, I OFF , DIBL and I ON ) using two state-of-the-art in-house-build 3-D simulation tools based on the finite element method. Quantum-corrected 3-D drift-diffusion simulations are employed for variability studies in the sub-threshold region while, in the on-region, we use quantum-corrected 3-D ensemble Monte Carlo simulations. The In 0.53 Ga 0.47 As FinFET is more resilient to the FER and MGW variability in the sub-threshold compared to the Si FinFET due to a stronger quantum carrier confinement present in the In 0.53 Ga 0.47 As channel. However, the on-current variability is between 1.1-2.2 times larger for the In 0.53 Ga 0.47 As FinFET than for the Si counterpart, respectively.

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Section: Finfet Modellingmentioning

confidence: 62%

“…Variability of transistor characteristics is not only a problem that mainly affects the device fabrication process but it has become an universal concern affecting CMOS and SRAM [3] scaling and perturbing digital logic circuits [4]. New design processes are require to incorporate this phenomena at every level [5].…”

Section: Introductionmentioning

confidence: 99%

Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

Seoane

Indalecio

Aldegunde

et al. 2016

IEEE Trans. Electron Devices

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“…Although the mechanisms behind BTI is still somewhat controversial, yet the most likely explanation is that it is caused by trap generations at the Si − SiO 2 interface and in the oxide of the transistors [16], [18], [20]. The devicelevel trapping-detrapping (TD) model developed in [21], which has been validated against silicon and is widely used in the community, captures the details of the stress and passive recovery physically.…”

Section: A Bti Wearout and Recovery Basicsmentioning

confidence: 99%

“…Reversible vs. Irreversible Wearout 1) Physics Perspective -Fast Traps vs. Slow Traps: Based on the trapping-detrapping theory [16], [18], the charge carriers need to gain sufficient kinetic energy to overcome a potential barrier necessary to break an interface state to be captured in the traps during trapping process. Here we define fast traps as those traps that have a high probability of trapping the charge carriers.…”

Section: Frequency Dependence Of Wearout and Recoverymentioning

confidence: 99%

“…While passive recovery is usually slow and unpredictable, and it cannot be used to reduce margins effectively, thus it is sometimes even ignored when modeling wearout phenomena. Besides, even recoverable wearout, like BTI, usually has an irreversible part that can't be recovered within a reasonable time [16], [17]. Thus these irreversible components left by passive recovery will keep accumulating over the rest of the lifetime.…”

Section: Introductionmentioning

confidence: 99%

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Implications of accelerated self-healing as a key design knob for cross-layer resilience

Guo

Stan

2017

Integration

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In this paper we propose a cross-layer accelerated self-healing (CLASH) system which "repairs" its wearout issues in a physical sense through accelerated and active recovery, by which wearout can be reversed while actively applying several accelerated self-healing techniques, such as high temperature and negative voltages. Different from previous solutions of coping with wearout issues (e.g. BTI) by "tolerating", "slowing down" or "compensating", which still leave the irreversible (permanent) wearout component unchecked, the proposed solution is able to fully avoid the irreversible wearout through periodic rejuvenation, and this is inspired by the explored frequency dependent behaviors of wearout and (accelerated and active) recovery based on measurements on FPGAs. We demonstrate a case where the chip can always be brought back to the fresh status by employing a pattern of 31-hour regular operation (under room temperature and nominal voltage) followed by a 1-hour accelerated selfhealing (under high temperature and negative voltage). The proposed system integrates the notions of accelerated self-healing across multiple layers of the system stack. At the circuit level, a negative voltage generator and heating elements are designed and implemented; at the architecture level, the core can be allocated in a way such that the dark silicon or redundant resources can be healed by active elements; at the system level, right balance of stress and accelerated/active recovery can be employed by the system scheduler to fully mitigate the wearout; various wearout sensors act as the media between different layers. Overall, these techniques work together to guarantee that the whole system performs for more of the time at higher levels of performance and power efficiency by fully taking advantage of the extra opportunities enabled by the accelerated self-healing.

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Introduction to Wearout

Guo

Stan

2019

Circadian Rhythms for Future Resilient Electronic Systems

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Cross-Layer Modeling and Simulation of Circuit Reliability

Cited by 51 publications

References 41 publications

Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

Implications of accelerated self-healing as a key design knob for cross-layer resilience

Introduction to Wearout

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