Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction

Abstract

<p>Today's data-centric applications are incompatible with the predominant compute-centric computer architectures. The small on-chip memories of compute-centric computer architecture demand many energy-costly data transfers exposing the von-Neumann bottleneck. The Ferroelectric Field-Effect Transistor (FeFET) is an emerging Non-Volatile Memory technology enabling novel data-centric architectures that go far beyond von-Nuemann principles. FeFETs are very promising for a wide range of applications starting from on-chip memories to in-memory computing and even neuromorphic computing. Nevertheless, FeFET devices exhibit significant variations that can severely restrict their applicability. Temperature further exacerbates variation effects because it degrades ferroelectric parameters. Hence, it is indispensable to investigate and model design-time variations, run-time variations, and stochastic variations due to spatial fluctuation of ferroelectric domains under different temperatures. Dual-port FeFET has been recently proposed and demonstrated as novel structure that offers for the first time disturb-free read operation along with larger memory window (MW) compared to conventional FeFETs. However, all of the before-mentioned types of variations are amplified in such a new structure. In this work, the impact of temperature variation is analyzed for dual-port FeFETs for the first time in a cross-layer manner starting from the device level to the circuit/system levels and compared to conventional FeFET. We focus in our analysis on Hyperdimensional Computing (HDC), which is an emerging type of machine learning algorithm, that is being executed on top of FeFET-based in-memory circuits that perform efficient Hamming distance (i.e., similarity) computations. Through our cross-layer framework, we demonstrate the serious impact of variation on FeFET reliability despite the significant increase in the MW that dual-port FeFET offers. Even HDC is affected, despite its remarkable robustness against errors. All in all, our work reveals that a larger MW at the device level does not necessarily translate to benefits at the application level. Hence, investigating and modeling variability effects in a cross-layer manner is indispensable.</p>

Cryogenic Brain-inspired Hyperdimensional In-Memory Computing using 5nm Ferroelectric FinFET

“…However, calculating the HD of an entire vector cannot be achieved in a single block due to its complexity. Particularly, differentiating the HD over 8 bits is difficult as it needs higher precision sense amplifiers 48 . Increasing the number of HD bits increases the overlap in the distribution of operational latencies, consequently widening the spread of diagonal probabilities in the confusion matrix.…”

“…This has a notable impact on circuit-level analysis (TCAM array). To cope with this, an approach divides each class hypervector of size d into d/b TCAM blocks, each storing b bits 48 . Within the TCAM array, rows store language class hypervectors.…”