Crossbar based Processing in Memory Accelerator Architecture for Graph Convolutional Networks

Challapalle, Nagadastagiri; Swaminathan, Karthik; Chandramoorthy, Nandhini; Narayanan, Vijaykrishnan

doi:10.1109/iccad51958.2021.9643465

Cited by 15 publications

(5 citation statements)

References 30 publications

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“…• Fixed Function Accelerators, specialized for specific tasks, maximize energy efficiency when targeting specialized kernels [57]. While excelling in performance and energy, they lose efficiency when generalized for multiple computations.…”

Section: B Background On Domain-specific Architectures 1) Overview Of...mentioning

confidence: 99%

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey

Yusuf,

Adegbija,

Gajaria

2024

IEEE Access

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In recent years, the rapid growth of big data and the increasing demand for high-performance computing have fueled the development of novel computing architectures. Among these, in-memory computing architectures that leverage the high-density and low-latency nature of modern memory technologies have emerged as promising solutions for domain-specific computing applications. STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) is one such in-memory computing technology that holds great potential for this field due to its non-volatility, high endurance, and low power consumption. In this survey paper, we aim to provide a comprehensive overview of the state-of-the-art in STT-MRAM-based domainspecific in-memory computing (DS-IMC) architectures. We examine the challenges, opportunities, and trade-offs associated with these architectures from the perspective of various application domains, like machine learning, image and signal processing, and data encryption. We explore different experimental research tools used in studying these architectures, guidelines for efficiently designing them, and gaps in the state-of-the-art that necessitate future research and development.INDEX TERMS domain-specific architectures, in-memory computing, spin-transfer torque RAM.

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Section: B Background On Domain-specific Architectures 1) Overview Of...mentioning

confidence: 99%

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey

Yusuf,

Adegbija,

Gajaria

2024

IEEE Access

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“…The high density and complexity of GCNs make the on-chip communication for IMC-based accelerators even more critical. Authors in [30,31] proposed an IMC-based accelerator for GCN. However, these technique does not address the issue of the on-chip communication performance of GCN accelerators.…”

Section: Related Workmentioning

confidence: 99%

COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks

Mandal,

Krishnan,

Goksoy

et al. 2022

Preprint

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Graph convolutional networks (GCNs) have shown remarkable learning capabilities when processing graphstructured data found inherently in many application areas. GCNs distribute the outputs of neural networks embedded in each vertex over multiple iterations to take advantage of the relations captured by the underlying graphs. Consequently, they incur a significant amount of computation and irregular communication overheads, which call for GCN-specific hardware accelerators. To this end, this paper presents a communicationaware in-memory computing architecture (COIN) for GCN hardware acceleration. Besides accelerating the computation using custom compute elements (CE) and in-memory computing, COIN aims at minimizing the intra-and inter-CE communication in GCN operations to optimize the performance and energy efficiency. Experimental evaluations with widely used datasets show up to 105× improvement in energy consumption compared to state-of-the-art GCN accelerator.

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“…PIM-GCN. PIM-GCN [72] is the first in-memory accelerator for GCN and demonstrates the mapping of GCN inference on the ReRAM crossbar architecture. The compute and memory access characteristics of GCN are different from the graph analytics and convolutional neural networks.…”

Section: Pim-based Graph Learning Acceleratorsmentioning

confidence: 99%

“…The selection of which data should be mapped on the ReRAM influences the data and writes movement overhead significantly. Unlike the previous work PIM-GCN [72] that fixed the static data on the ReRAM, TARe [75] proposes a task adaptive selection algorithm that selects the static data according to the task and a ReRAM in situ accelerator that supports weight-static, data-static, and hybrid execution mode. For a graph learning workload, the task adaptive selection algorithm first selects the static data and decides the sparse or dense mapping mode.…”

Section: Pim-based Graph Learning Acceleratorsmentioning

confidence: 99%

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Software Systems Implementation and Domain-Specific Architectures towards Graph Analytics

Jin

Zhao

et al. 2022

Intell Comput

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Graph analytics, which mainly includes graph processing, graph mining, and graph learning, has become increasingly important in several domains, including social network analysis, bioinformatics, and machine learning. However, graph analytics applications suffer from poor locality, limited bandwidth, and low parallelism owing to the irregular sparse structure, explosive growth, and dependencies of graph data. To address those challenges, several programming models, execution modes, and messaging strategies are proposed to improve the utilization of traditional hardware and performance. In recent years, novel computing and memory devices have emerged, e.g., HMCs, HBM, and ReRAM, providing massive bandwidth and parallelism resources, making it possible to address bottlenecks in graph applications. To facilitate understanding of the graph analytics domain, our study summarizes and categorizes current software systems implementation and domain-specific architectures. Finally, we discuss the future challenges of graph analytics.

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Crossbar based Processing in Memory Accelerator Architecture for Graph Convolutional Networks

Cited by 15 publications

References 30 publications

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey

COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks

Software Systems Implementation and Domain-Specific Architectures towards Graph Analytics

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