Crossing the architectural barrier: Evaluating representative regions of parallel HPC applications

Abstract

Exascale computing will get mankind closer to solving important social, scientific and engineering problems. Due to high prototyping costs, High Performance Computing (HPC) system architects make use of simulation models for design space exploration and hardware-software co-design. However, as HPC systems reach exascale proportions, the cost of simulation increases, since simulators themselves are largely single-threaded. Tools for selecting representative parts of parallel applications to reduce running costs are widespread, e.g., BarrierPoint achieves this by analysing, in simulation, abstract characteristics such as basic blocks and reuse distances. However, architectures new to HPC have a limited set of tools available.In this work, we provide an independent cross-architectural evaluation on real hardware-across Intel and ARM-of the BarrierPoint methodology, when applied to parallel HPC proxy applications. We present both cases: when the methodology can be applied and when it cannot. In the former case, results show that we can predict the performance of full application execution by running shorter representative sections. In the latter case, we dive into the underlying issues and suggest improvements. We demonstrate a total simulation time reduction of up to 178x, whilst keeping the error below 2.3% for both cycles and instructions. This is an accepted version of the IEEE published article available at http://ieeexplore.ieee.org/abstract/document/7975275/

Efficient thread‐to‐core mapping alternatives for application‐level redundant multithreading

“…A set of studies focus on workload characterization and phase-detection using homogeneous and heterogeneous CMPs in literature. [25][26][27][28] Eeckhout et al 25 found that architecture-independent characteristics, such as instruction-mix, register-dependencies, working-set size, and branch predictability can be used to find the similarity among single-threaded applications. Sawalha et al 26 proposed to schedule threads not only observing phase-change of an application running on heterogeneous CMPs also re-use the information for later phases to reduce the sampling count.…”

“…A set of studies focus on workload characterization and phase‐detection using homogeneous and heterogeneous CMPs in literature 25‐28 . Eeckhout et al 25 found that architecture‐independent characteristics, such as instruction‐mix, register‐dependencies, working‐set size, and branch predictability can be used to find the similarity among single‐threaded applications.…”

“…Becchi and Crowly 27 proposed using a dynamic thread assignment policy for heterogeneous cores based on IPC values. Ferrorón et al 28 used the representative regions between barrier points for multithreaded HPC applications to predict cycles, instructions, and cache usage behaviors. Our study has similarities and differences with those studies.…”

ARM HPC Ecosystem and the Reemergence of Vectors

“…Apart from assessing requirements and enabling software and future technologies, ARM and its partners have focused on research for future processor technologies including architecture and micro-architecture solutions for high-end systems with a focus on HPC. Simulation tools are critical for research and development and several new methodologies have been proposed and implemented to enable simulation of large HPC systems [15,12,11,10,8].…”