Crosstalk-aware TSV-buffer Insertion in 3D IC

Chen, Yen‐Hao; Huang, Po-Chen; Chen, Fu-Wei; Wu, Allen C.-H.; Hwang, TingTing

doi:10.1109/socc46988.2019.1570539111

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2021

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“…Due to the rapid increase in the integration scale, crosstalk between TSVs is becoming a crucial issue as the TSV size and pitch shrinks and can result in serious signal integrity issues including the rise of noise margin and bit error rate. [4][5][6][7] Many analytical capacitive models have been proposed to evaluate the crosstalk in TSV arrays. These models are either based on the extraction of circuit parameters [8][9][10][11][12][13][14] such as resistance, capacitance, inductance, transconductance, or on field simulations 4,15,16) to examine the S parameters, etc.…”

Section: Introductionmentioning

confidence: 99%

Characterization of corner/edge effects of through silicon via arrays and layout optimization in 3D integrated circuits

Zhao

Sun

et al. 2021

Jpn. J. Appl. Phys.

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Signal integrity in high density through silicon via (TSV) has become a key concern in 3D integrated circuits design as its continuous scaling down. In this paper, the corner/edge effect of TSV arrays is proven to be non-neglectable and is characterized by coupling capacitance, mutual inductance, S parameter, and maximum noise respectively. The 6C static shielding method (X. Cui et al., ICEPT, 2018, p. 944) is improved by inserting ground TSVs at the array corners according to our evaluation. At last, we proposed three layout optimization rules for TSV interposer design to generate a more balanced electromagnetic shielding and to achieve better signal integrity.

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