Crosstalk cancelling voltage‐mode driver for multi‐Gbps parallel DRAM interface

Kim, Young-Hoon; Yoo, Changsik

doi:10.1002/cta.2003

Cited by 1 publication

(1 citation statement)

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“…The volatile memory of static random access memory (SRAM) and dynamic random access memory (DRAM) are widely used in computing systems [1][2][3][4]. Scaling bulk CMOS SRAM technology for on-chip caches beyond the 22 nm node results in high leakage power consumption, performance degradation, and instability due to process variations [5,6].…”

Section: Introductionmentioning

confidence: 99%

Low-Power Single Bitline Load Sense Amplifier for DRAM

Dai,

Lu,

et al. 2023

Electronics

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With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing performance or difficulties in the smaller footprint of the DRAM capacitor. Since optimizing the circuit of sense amplifier (SA) is an efficient method to reduce energy consumption, we propose two single bitline load sense amplifier (SBLSA) circuits, i.e., a redundant voltage discharged SBLSA (RVD-SBLSA) circuit and a bit aware SBLSA (BA-SBLSA) circuit, to improve conventional and single bitline write (SBW) circuits. The RVD-SBLSA circuit utilizes a clamp diode to discharge redundant voltage over VDD/2 with an additional working stage. The BA-SBLSA circuit abandons the single bitline load (SBL) circuit during read and write ‘1’ operations. The RVD-SBLSA circuit can offer the lowest total energy consumption, and the BA-SBLSA circuit can make a better balance between energy consumption and latency. Through the simulation results, the proposed circuits can efficiently reduce energy consumption or balance energy consumption and latency and show huge potentials in very large-scale integrated circuits.

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