Crosstalk in VLSI partially coupled interconnect structures, a comprehensive evaluation

Abstract

In this paper, the investigation methodology for crosstalk evaluation in two groups of interconnect structures in nano scale VLSI circuits is presented. The first group consists of a victim line shorter than the aggressor line. We show that when the interconnects parameters are chosen properly, and the victim line stays at the end part of the aggressor line, the crosstalk noise can be reduced up to 86% in comparison to the case that the victim line is placed at the beginning of the other line. The interconnects in the second group are identical and partially coupled. The results obtained from an extensive study show that by choosing optimum values, the crosstalk noise can be reduced up to 92% when the victim line stays ahead of the aggressor line, in comparison to the case that it is placed behind it. IntroductionAs technology scales down to deep submicron regions in VLSI circuits, the interconnects width and spacing decrease in a way that their adverse effects cannot be neglected and they play a key role in the performance of the circuits [1,4]. Thus, the crosstalk noise between coupled lines will no longer be negligible. Moreover, it causes the delay and power to increase, while the performance and reliability of circuits to decline. To reduce the crosstalk noise, different methods have been proposed including shielding method [5,7], repeater insertion [8-10], device sizing [11,12], various routing techniques [13][14][15] and input coding [16,17].The crosstalk noise in interconnect structures with different lengths and partially coupled lines have not been thoroughly investigated. This paper addresses a methodology for evaluation of the crosstalk noise and delay in structures with different positions of a victim line relative to a longer or identical aggressor line.

Differential symmetry principle for differential crosstalk cancellation

“…Nowadays efforts of crosstalk mitigation is focused on changing the interconnects design, such as wider spacing for the trace routing, more shielding for socket/connector [2][3][4] etc. However, these approaches can result in larger board size or increased board layer count with a higher component cost.…”