Crosstalk Interconnect Noise Optimization Technique Using Wire Spacing and Sizing for High Speed Integrated Circuits

Abstract

Abstract-Scaling the minimum feature size of VLSI circuits to sub-quarter micron and its clock frequency to 3GHz has caused crosstalk noise to become a serious problem that degrades the performance and reliability of high speed integrated circuits. This paper presents an efficient method for computing the capacitive crosstalk in sub-quarter micron VLSI circuits. In this paper, we present a complete analytical crosstalk noise model which incorporates all physical properties including victim and aggressor drivers, distributed RC characteristics of interconnects and coupling locations in both victim and aggressor lines. We present closed-form analytical expressions for peak noise and noise width to estimate on-chip crosstalk noise and also shown that crosstalk can be minimized by wire spacing and wire sizing optimization technique. These models are verified for various deep submicron technologies.Index Terms-Aggressor, Coupling, Crosstalk, Interconnect noise, Wire spacing, I. INTRODUCTIONAdvancement in the field of very large scale integration (VLSI) have lead to a decrease in device geometries (deep submicron technology), high device densities, high clock rates, and thus small signal transition times. Thus, interconnection lines that were once considered to be electrically isolated can now interfere with each other and have an important impact on system performance and correctness. One such interaction caused by parasitic coupling between wires is known as crosstalk. If not carefully considered during design validation, crosstalk can cause extra signal delay, logic hazards, and even circuit malfunction. Accurate modeling and simulation of interconnect delay due to crosstalk thus becomes increasingly important in the design of high-performance integrated circuits.The net on which noise is being induced is called the victim net whereas the net that induces this noise is called the aggressor net. Crosstalk noise not only leads to modified delays [2], [ 3] but also to potential logic malfunctions [4], [ 5]. To be able to deal with the challenges brought by this recently emerging phenomenon, techniques and tools to estimate and avoid crosstalk noise problems should be incorporated into the IC design cycle from the early stages. Any such tool requires fast yet accurate crosstalk noise models both to estimate noise and also to see the effects of Manuscript received September 19, 2011; revised December 3, 2011. P. V. Hunagund is with the Department of Applied Electronics, Gulbarga University, Gulbarga, India (e-mail:prabhakar.hunagund@gmail.com).A. B. Kalpana is with the Electronics and Communication Engineering Department, Bangalore Institute of Technology, Bangalore, India (e-mail: abkalpana@gmail.com).various interconnect and driver parameters on noise. Several papers, which propose crosstalk models, can be found in recent literature. In [6], telegraph equations are solved directly to find a set of analytical formulae for peak noise in capacitively coupled bus lines. [7] derives bounds for crosstalk noise using a lumpe...