Cryo-CMOS for quantum computing

Charbon, Edoardo; Foti, Sebastiano; Vladimirescu, Andrei; Homulle, Harald; Visser, Stefan; Lin, Shan; Incandela, Rosario

doi:10.1109/iedm.2016.7838410

Cited by 208 publications

(94 citation statements)

References 17 publications

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“…The additional power consumed by the FET at deep-cryogenic temperatures as a result of ∆SS is crucial for the desired scalability of quantum computers that is expected from co-integration of spin qubits in Si with FET-based control circuits. [23][24][25][26][27][28][29][30][31][32][33][34] a) Electronic mail: arnout.beckers@epfl.ch…”

Section: Introductionmentioning

confidence: 99%

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

Beckers

Jazaeri

Enz

2020

IEEE Electron Device Lett.

162

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Measurements in field-effect transistors have indicated that the Boltzmann thermal limit of the subthreshold swing, (k B T /q) ln 10, is not followed down to deep-cryogenic temperatures. Instead, there is a nonlinear deviation from this limit which cannot be explained with the present theory. In this paper, we derive a new theory which resolves this discrepancy by including the source-drain tunneling through a band tail. We demonstrate that the additional tunneling component of the current becomes dominant over the diffusion current at a sufficiently low cryogenic temperature. A band tail in the electrostatics, with only diffusion transport, does not explain the excess subthreshold swing at deep-cryogenic temperatures, neither does only self-heating, nor does a nonuniform density of interface traps in the bandgap with Fermi-Dirac occupation. The proposed theory is experimentally validated with our measurements in advanced CMOS technology down to 4.2 K. Finally, we assess the obtained densities of interface traps in the presence of band-tail tunneling.

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Section: Introductionmentioning

confidence: 99%

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

Beckers

Jazaeri

Enz

2020

IEEE Electron Device Lett.

162

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“…For single-ended N-stages CMOS ring oscillators, assuming that the thermal noise sources of every inverter are uncorrelated and that the waveform (hence the ISF) of all nodes are the same except for a phase-shift, the total phase noise is N times the value given by (1). Taking only these inevitable noise sources into account, the expression for phase noise is given by [6]:…”

Section: Circuit Descriptionmentioning

confidence: 99%

“…With the development of quantum computing, the wiring requirements between the cryogenic quantum processor and the room temperature (RT) read-out controller can be both expensive and unreliable [1]. As an alternative, a cryogenic electronic interface that consists of control, interaction and read-out stages has been proposed.…”

Section: Introductionmentioning

confidence: 99%

0.18μm CMOS Ring Oscillator at Liquid Helium Temperature

Luo

et al. 2019

2019 IEEE 3rd International Conference on Circuits, Systems and Devices (ICCSD)

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This paper presents low power dissipation, low phase noise ring oscillators (ROs) based on Semiconductor Manufacturing International Corporation (SMIC) 0.18μm CMOS technology at liquid helium temperature (LHT). First, the characterization and modelling of CMOS at LHT are presented. The temperature-dependent device parameters are revised and the model then shows good agreement with the measurement results. The ring oscillator is then designed with energy efficiency optimization by application of forward body biasing (FBB). FBB is proposed to compensate for the threshold voltage (VTH) shift to preserve the benefits of the enhancement of the carrier mobility at 4.2K. The delay per stage (τp), the static current (ISTAT), the dynamic current (IDYN), the power dissipation (P) and the phase noise (L(foff)) are analyzed at both 298 K and 4.2 K, with and without FBB. The performance of the designed RO in terms of speed (τp=179ps), static current (23.55nA/stage), power dissipation (2.13μW) and phase noise (-177.57dBc/Hz@1MHz) can be achieved at 4.2K with the supply voltage (VDD) reduced to 0.9V.

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“…In recent years, hardware interfaces based on advanced CMOS technologies that operate at cryogenic temperature so as to ensure proximity to qubits have been proposed and discussed [6][7][8][9]. Bulk Si MOSFET [10][11][12][13] and other basic circuits such as Ring Oscillators (ROs) [11] and an FPGA (Field-Programmable Gate Array) [14] were characterized down to H. Bohuslavskyi 4K. Despite a significant reduction of subthreshold swing (SS) and improvement of carrier mobility at low temperature, some limitations have been raised on bulk Si technologies.…”

Section: Introductionmentioning

confidence: 99%

Cryogenic Characterization of 28-nm FD-SOI Ring Oscillators With Energy Efficiency Optimization

Bohuslavskyi

Barraud

Barral

et al. 2018

IEEE Trans. Electron Devices

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Extensive electrical characterization of ring oscillators (ROs) made in high-κ metal gate 28nm Fully-Depleted Silicon-on-Insulator (FD-SOI) technology is presented for a set of temperatures between 296 and 4.3K. First, delay per stage (τ P ), static current (I STAT ), and dynamic current (I DYN ) are analyzed for the case of the increase of threshold voltage (V TH ) observed at low temperature. Then, the same analysis is performed by compensating V TH to a constant, temperature independent value through forward body-biasing (FBB). Energy efficiency optimization is proposed for different supply voltages (V DD ) in order to find an optimal operating point combining both high RO frequencies and low power dissipation. We show that the Energy-Delay product (EDP) can be significantly reduced at low temperature by applying a forward body bias voltage (V FBB ). We demonstrate that outstanding performance of RO in terms of speed (τ p =37ps) and static power (7nA/stage) can be achieved at 4.3K with V DD reduced down to 0.325V.

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Cryo-CMOS for quantum computing

Cited by 208 publications

References 17 publications

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

0.18μm CMOS Ring Oscillator at Liquid Helium Temperature

Cryogenic Characterization of 28-nm FD-SOI Ring Oscillators With Energy Efficiency Optimization

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