Cryo-CMOS Interfaces for Large-Scale Quantum Computers

Foti, Sebastiano; Dijk, Jeroen P. G. van; Hart, Pascal A. lt; Patra, Bishnu; Staveren, Job van; Xue, Xiangxin; Almudéver, Carmen G.; Scappucci, Giordano; Veldhorst, Menno; Vandersypen, L. M. K.; Vladimirescu, Andrei; Pellerano, Stefano; Babaie, Masoud; Charbon, Edoardo

doi:10.1109/iedm13553.2020.9372075

Cited by 16 publications

(13 citation statements)

References 16 publications

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“…In the case of CMOS sensors, another related challenge for deep-cryogenic operation is the usability of electronics in these devices at sub-Kelvin temperatures. The detailed properties of the electronics depend on target applications, and circuits designed to operate above 100 K may not perform well below 1 K. Numerous studies in the literature have been focusing on characterizing CMOS electronics designed for operation at around 4 K, and CMOS control and readout devices have been built to operate at these temperatures in quantum computing applications [41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58], or recently even as low as ∼ 0.05 K for use with quantum dots [59]. It would be instructive for the future experimental studies of the detector proposed in this paper to test simple CMOS circuits designed for operation at 4 K at the lower temperatures of the cold plate and the still flange.…”

Section: Jinst 18 P12005mentioning

confidence: 99%

Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors

Sarıca

2023

J. Inst.

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Recent studies in quantum computing have shown that quantum error correction with large numbers of physical qubits are limited by ionizing radiation from high-energy particles. Depending on the physical setup of the quantum processor, the contribution of muons from cosmic sources can constitute a significant fraction of these interactions. As most of these muons are difficult to stop, we perform a conceptual study of a two-layer silicon pixel detector to tag their hits on a solid-state quantum processor instead. With a typical dilution refrigerator geometry model, we find that efficiencies greater than 50% are most likely to be achieved if at least one of the layers is operated at the deep-cryogenic (<1 K) flanges of the refrigerator. Following this finding, we further propose a novel research program that could allow the development of silicon pixel detectors that are fast enough to provide input to quantum error correction algorithms, can operate at deep-cryogenic temperatures, and have very low power consumption.

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Section: Jinst 18 P12005mentioning

confidence: 99%

Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors

Sarıca

2023

J. Inst.

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“…This imposes a significant blockage to scaling up existing quantum computers, making it profoundly challenging, if not infeasible, to reach the targeted 10 3 qubits to 10 6 qubits range. To overcome this challenge, researchers have proposed moving the control circuits close to the qubits and operating them at cryogenic temperatures [4][5][6][7][8][9][10] . This will open the door for efficient data processing as well as rapidly carrying out the necessary classification to convert readout data to the digital world along with performing the required error corrections 4,5 .…”

Section: Introductionmentioning

confidence: 99%

Cryogenic Brain-inspired Hyperdimensional In-Memory Computing using 5nm Ferroelectric FinFET

Parihar,

Kumar,

Chatterjee

et al. 2024

Preprint

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The pursuit of large-scale quantum computing has captivated the scientific community, and the potential of cryogenic circuits using mature CMOS technologies represents a significant step forward in this quest. Nevertheless, the operation of circuits at cryogenic temperatures poses significant challenges due to the strict power and timing constraints. These challenges are compounded by the well-known Von Neumann bottleneck that plays a major role in limiting the throughput and energy efficiency of modern computing systems. To overcome such a bottleneck, In-Memory Computing (IMC) is rapidly emerging as a promising solution for creating hardware accelerators that go far beyond Von Neumann principles, offering substantial efficiency improvements. In this work, we investigate the effectiveness of cryogenic brain-inspired hyperdimensional IMC using emerging Ferroelectric (FE) technologies at the 5 nm node. To achieve that, we begin by characterizing commercial 5 nm FinFETs from room temperature (300 K) down to cryogenic temperature (10 K). Then, we carefully calibrate the first industry-standard cryogenic-aware compact model (BSIM-CMG) to accurately reproduce the measurements. Afterward, we incorporate a physics-based FE model within the BSIM-CMG model and calibrated it against FE capacitor measurements to realize Fe-FinFET devices operating from 300 K down to 10 K. Then, as proof of concept, we focus on 1×8 Ternary Content Addressable Memory (TCAM) array that we use to perform the language classification using brain-inspired hyperdimensional IMC. Our comprehensive analysis spans from investigating the delay, power, and energy efficiency of IMC-based TCAM all the way up to calculating error probabilities in which we compare the figure of merits obtained from the emerging Fe-FinFET against classical FinFET-based IMC.

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“…Authors in [6] reported the use of 128 ×64 and 64 ×64 SRAM array at different layers in quantum error correction. Apart from error correction, memories are also required to store the intermediate signals to control and readout the qubits [22]- [24]. Since performance and power are of the utmost importance for this kind of data storage, memory technologies other than SRAM are not suitable to be used as storage elements.…”

Section: Introductionmentioning

confidence: 99%

Unveiling Enhanced Trade-offs in SRAM-based Memory Arrays for Cryogenic CMOS Technology

Parihar,

Pahwa,

Mohammad

et al. 2024

Preprint

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Cryo-CMOS Interfaces for Large-Scale Quantum Computers

Cited by 16 publications

References 16 publications

Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors

Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors

Cryogenic Brain-inspired Hyperdimensional In-Memory Computing using 5nm Ferroelectric FinFET

Unveiling Enhanced Trade-offs in SRAM-based Memory Arrays for Cryogenic CMOS Technology

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