Cryogenic Characerization and Modeling of Standard CMOS down to Liquid Helium Temperature for Quantum Computing

Abstract

Cryogenic characterization and modeling of 0.18µm CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias conditions at temperatures ranging from 300K down to 4.2K. We extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. In addition to their I-V characteristics, threshold voltage(V th ) values, on/off current ratio, transconductance of the MOS transistors, and resistors on chips are measured at temperatures from 300K down to 4.2K. A simple subcircuit was built to correct the kink effect. This work provides experimental evidence for implementation of cryogenic CMOS technology, a valid industrial tape-out process model, and promotes the application of integrated circuits in cryogenic environments, including quantum measurement and control systems for quantum chips at very low temperatures.

Cryogenic characterization of 180 nm CMOS technology at 100 mK

“…We apply a basic BSIM3 model to try to replicate the behavior of our devices at cryogenic temperatures, tuning a limited set of the model parameters to fit the measurements [7]. The BSIM3 model is not designed to work below around 220 K, but previous work has shown it is possible to phenomenologically tune the model parameters to work down to 77 K [8,9], and possibly even down to 4 K [10]. We tune the V th0 , K 1 , U A , and U B parameters using measurements from one device size and then apply the resulting model to other sizes for comparison.…”