Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K

Parihar, Shivendra Singh; Santen, Victor M. van; Thomann, Simon; Pahwa, Girish; Chauhan, Yogesh Singh; Amrouch, Hussam

doi:10.1109/tcsi.2023.3278351

Cited by 15 publications

(5 citation statements)

References 37 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Cooling down to cryogenic temperatures affects the characteristics of short-channel NMOS and PMOS transistors by increasing their threshold voltage V th (100-200 mV), subthreshold slope (∼3× steeper), and carrier mobility (∼2× for low-field mobility) [18], [19], [32], [57], [58], [59], [60], [61]. Additionally, the mismatch between devices increases, as shown in [62] and [63] for 40-nm bulk CMOS and 28-nm bulk CMOS, respectively, interconnect resistance drops (∼30%) [64], and the capacitance of source/drain junctions decreases due to wider depletion regions due to freeze-out [19].…”

Section: Cryo-cmos Device Behaviormentioning

confidence: 99%

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Damsteegt,

Overwater,

Babaie

et al. 2024

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

The interface electronics needed for quantum processors require cryogenic CMOS (cryo-CMOS) embedded digital memories covering a wide range of specifications. To identify the optimum architecture for each specific application, this article presents a benchmark from room temperature (RT) down to 4.2 K of custom SRAMs/DRAMs in the same 40-nm CMOS process. To deal with the significant variations in device parameters at cryogenic temperatures, such as the increased threshold voltage, lower subthreshold leakage, and increased variability, the feasibility of different memories at cryogenic temperature is assessed and specific guidelines for cryogenic memory design are drafted. Unlike at RT, the 2T low-thresholdvoltage (LVT) DRAM at 4.2 K is up to 2× more power efficient than both SRAMs for any access rate above 75 kHz since the lower leakage increases the retention time by 40 000×, thus sharply cutting on the refresh power and showing the potential of cryo-CMOS DRAMs in cryogenic applications.

show abstract

Section: Cryo-cmos Device Behaviormentioning

confidence: 99%

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Damsteegt,

Overwater,

Babaie

et al. 2024

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…The steeper sub-threshold characteristics at the cryogenic temperature also improves static noise margin of the inverter and the SRAM cell at lower V DD compared to the room temperature, as demonstrated in [4], [5]. Further, the power, delay and reliability of 5nm FinFET SRAM circuits has been studied at deep cryogenic temperatures [6]. A recent theoretical study demonstrated 4× improvement in performance-per-watt at the processor level (Arm Cortex-A53) at cryogenic temperatures [7].…”

Section: Introductionmentioning

confidence: 98%

“…These predictive model cards are scalable with temperatures, and also scalable with device engineering (e.g., V DD and V TH tuning) and major process variations. It is worth noting that [6] has created model cards for the 5nm FinFET technology node. However, our work stands out in that we have expanded the flexibility of these model cards to predict the behavior of CMOS logic circuits at cryogenic temperatures.…”

Section: Introductionmentioning

confidence: 99%

Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing

Gaidhane,

Saligram,

Chakraborty

et al. 2023

IEEE J. Explor. Solid-State Comput. Devices Circuits

View full text Add to dashboard Cite

Cryogenic operation of CMOS transistors (i.e., cryo-CMOS) effectively brings an ultra-steep sub-threshold slope and ultra-low leakage, enabling high energy efficiency with appropriate tuning of threshold voltage and supply voltage. On the other hand, cryo-CMOS suffers from elevated sensitivity to process and voltage variations. To facilitate early-stage design exploration, we develop predictive BSIM-CMG model cards, which are calibrated with 14nm TCAD simulation and our experimental FinFET data from 300K to 77K. These models are scalable with temperatures from 300K down to 77K, device engineering and variations. Based on them, we benchmark various circuit examples to illustrate the tremendous potential of cryo-CMOS for energy-efficient computing, in the presence of process variations. For logic circuits, such as a canonical critical path, more than 15× reduction in total energy consumption is demonstrated at 77K for the iso-Delay condition, compared to the operation at the room temperature (RT). The presence of variations only has a marginal impact on energy efficiency, after threshold voltage and supply voltage are adaptively increased. For static noise margin (SNM), it is consistently improved at 77K. However, the impact of variations on SNM is much more pronounced than that on logic circuits.

show abstract

“…Some first-principles and density functional theory (DFT) computational methods have been utilized to calculate the electrical properties of stacked NSs and have been employed to guide the design of stacked NS devices [ 11 , 12 ]. Unfortunately, although there have been some studies on the low-temperature characteristics of NS transistors for specific channel structures and customized processes [ 13 , 14 , 15 , 16 , 17 , 18 , 19 ], there is little research on the low-temperature carrier transport characteristics of NS transistors with a general structure using mainstream fabrication processes based on HK/MG-last technologies. Furthermore, data on the quantum transport characteristics and relative quantum dot operation behavior of NS devices are also lacking.…”

Section: Introductionmentioning

confidence: 99%

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process

Zhu,

Cao,

Wang

et al. 2024

Nanomaterials

View full text Add to dashboard Cite

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.

show abstract

Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K

Cited by 15 publications

References 37 publications

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS

Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process

Contact Info

Product

Resources

About