Cryogenic matching performance of 90 nm MOSFETs

Abstract

While the matching properties of MOSFETs have been extensively studied, the impact of temperature on matching remains poorly understood. Recent efforts at understanding the effects of temperature on matching [1,2] report improved matching at higher temperatures. Here, we examine the impact of cryogenic temperatures on the matching performance of a 90 nm bulk CMOS technology. Cryogenic operation improves many of the MOSFET performance metrics and cryogenic MOSFETs have been shown to achieve lower broadband noise at cryogenic temperatures [3], opening up the possibility of their application in radio astronomy that require very low noise. As suggested in [1], however, device matching could potentially degrade with cooling. In addition to the enhancement of columbic scattering and the associated variations due to dopant fluctuations [2], cryogenic temperatures impose additional variability due to incomplete ionization and enhanced quantum effects.In this work, nMOSFETs of multiple dimensions were layed-out in a common source/body configuration with separate drain and gate contacts. To conserve space, four devices of identical dimensions were placed at minimum distance from each other, constituting six identical device pairs (Figure 1). The devices to be measured were selected by the gate and drain biases. Linear transfer characteristics were measured at a drain-to-source voltage (V DS ) of 50 mV at a body bias of 0 V and -0.6 V. Threshold voltages were extracted using the constant current method at multiple fixed drain currents. A set of 30 device pairs was measured to ensure adequate statistics.The normalized peak transconductance (g m ) of discrete nMOSFETs of multiple device dimensions from the same technology node, as a function of temperature, is shown in Figure 2. As expected, the peak transconductance improves with cooling due to the improvement in mobility. In addition, MOSFETs with larger gate length show a larger improvement in peak g m due to their lower channel doping. The mismatch in threshold voltage (V T ) for three fixed drain currents (I D ) is shown in Figure 3. The V T mismatch decreases with increasing device dimensions (as expected) and increases with cooling (not as expected). Interestingly, the temperature sensitivity of the mismatch is a function of the drain current at which V T is extracted, and the temperature sensitivity decreases with increasing drain currents. In addition, the mismatch worsens with increasing substrate bias.Since current mismatch is a more relevant metric for many circuit applications, we have also included the V T mismatch for constant I D mismatch across temperature in Figure 3. For the same drain current ratio in subthreshold, the threshold voltage mismatch can be expressed as (assuming identical body factor across temperature):(1) Under strong inversion, for the same drain current mismatch, the required threshold voltage mismatch can be expressed as:(2)The more stringent requirement for threshold voltage matching with cooling is due to the improved subthreshold swing...

Effect of percolation path on temperature dependence of threshold voltage variability in bulk MOSFETs

“…For very large-scale quantum computing, it is strongly required that one understands the variability characteristics of cryo-CMOSs. The threshold voltage (V TH ) variability of bulk [1][2][3][4] and fully depleted silicon-on-insulator 5,6) MOSFETs has been measured and reported at cryogenic temperature (CT), and it has been shown that the random variability characteristics of MOSFETs at CT are not so different from those at RT. We have also reported the variability of key transistor parameters of bulk MOSFETs at CT. 7) However, detailed causes of variability at CT remain unclear.…”