Cryptographically Secure Pseudo-Random Number Generator IP-Core Based on SHA2 Algorithm

Baldanzi, Luca; Crocetti, Luca; Falaschi, Francesco; Bertolucci, Matteo; Belli, Jacopo; Fanucci, Luca; Saponara, Sergio

doi:10.3390/s20071869

Cited by 27 publications

(22 citation statements)

References 11 publications

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“…Depending on the nature of the entropy source, the randomness can be generated either in the analogue world (e.g., noise or sensors [6]) or in the digital world (e.g., Jitter). There are also examples in literature [7] of Cryptographically Secure Pseudo-Random Number Generator (CSPRNG); such circuits, however, requires a TRNG to work. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy.…”

Section: Introduction: Random Number Generation For Securitymentioning

confidence: 99%

True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

et al. 2021

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Random numbers are widely employed in cryptography and security applications. If the generation process is weak, the whole chain of security can be compromised: these weaknesses could be exploited by an attacker to retrieve the information, breaking even the most robust implementation of a cipher. Due to their intrinsic close relationship with analogue parameters of the circuit, True Random Number Generators are usually tailored on specific silicon technology and are not easily scalable on programmable hardware, without affecting their entropy. On the other hand, programmable hardware and programmable System on Chip are gaining large adoption rate, also in security critical application, where high quality random number generation is mandatory. The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array. After a preliminary study of literature and standards specifying requirements for random number generation, the design flow is illustrated, from specifications definition to the synthesis phase. Several solutions have been studied to assess their performances on a Field Programmable Gate Array device, with the aim to select the highest performance architecture. The proposed designs have been tested and validated, employing official test suites released by NIST standardization body, assessing the independence from the place and route and the randomness degree of the generated output. An architecture derived from the Fibonacci-Galois Ring Oscillator has been selected and synthesized on Intel Stratix IV, supporting throughput up to 400 Mbps. The achieved entropy in the best configuration is greater than 0.995.

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Section: Introduction: Random Number Generation For Securitymentioning

confidence: 99%

True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

et al. 2021

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“…It hinders utilizing it directly for the applications and further demands high system resources, which is unavailable in low power IoT devices. [140] This limitation is alleviated by the deterministic algorithm based Pseudo-Random Number Generator (PRNG) to generate the random bitstream. Cryptographically secure PRNG (CSPRNG) requires high entropy input seed meeting its security strength, and this seed determines its internal state making the random number generation unpredictable.…”

Section: True Random Number Generatormentioning

confidence: 99%

Application of Resistive Random Access Memory in Hardware Security: A Review

Rajendran

Banerjee

Chattopadhyay

et al. 2021

Adv Elect Materials

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today, with the low power embedded devices deployed for sensing, actuating and running intelligent decision-making algorithms. The advancement in wireless communication technologies such as WiFi, Bluetooth low energy, 4G-LTE, LoRaWAN and recently 5G millimeter wave communication coupled with huge boost in the computing capabilities enable these devices to exchange and process data both at the edge and cloud. This intelligent environment is now widely explored as the Internet of Things (IoT). One of the primary concerns in this development is to security. Most of the available protocols and encryption techniques for device authentication and data transfer are purely software measures, thus presenting an opportunity for a determined attacker to bypass those with higher computing power or uncover the secrets through information leakages in physical forms. Furthermore, software-driven security demands high system resources, which is unavailable in resource-constrained IoT devices, therefore necessitating robust hardware security solutions that can be integrated into those devices. On the other hand, globalization of the semiconductor industry supply chain mandates a careful auditing and trust management during the fabrication and system integration process, which can very well benefit from the inherent randomness in the manufacturing processes. Hence, hardware security research today predominantly focuses on designing security primitives that tap onto the manufacturing variations, thereby constructing primitives like true random number generator (TRNG), physical unclonable function (PUF), and cryptographic hash functions.The emerging nonvolatile memory (NVM) devices such as resistive random access memory (RRAM), spin-transfer torque magnetic random-access memory (STT-MRAM), spin-orbit torque magnetic random-access memory (SOT-MRAM), and ferroelectric field-effect transistors (FeFET) are currently explored for building beyond Von Neumann architectures. Among them, RRAM is well established today. It is a two-terminal device commonly known for its metal-insulator-metal structure. This device technology's strength is the available wide range of functional materials that can be engineered for reliable resistive switching. It includes binary transition metal oxides, 2D materials likeNowadays, advancements in the design of trusted system environments are relying on security provided by hardware-based primitives, while replacing resource-hungry software security measures. Emerging nonvolatile memory devices are promising candidates to provide the required hardware security functionalities at very low area-energy-runtime budget. Resistive random access memory (RRAM) offers high-density integration with outstanding performance among the state-of-the-art nonvolatile memory devices. The RRAM device technology is currently getting significant attention from both academia and industry for constructing beyond Von Neumann architectures. This technology's strength is its scalable two-terminal structure, the availability of wide range...

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“…Architectural design of a configurable (at synthesis level) ECC crypto-processor for NIST P-256 and/or NIST P-521 elliptic curves, developed in the framework of the European Processor Initiative together with other cryptographic hardware accelerators (AES, RNG [27,28], SHA [29]). The proposed architecture supports the most used cryptographic schemes based on ECC such as ECDSA, ECDH, ECIES and ECMQV.…”

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confidence: 99%

Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

et al. 2021

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Cybersecurity is a critical issue for Real-Time IoT applications since high performance and low latencies are required, along with security requirements to protect the large number of attack surfaces to which IoT devices are exposed. Elliptic Curve Cryptography (ECC) is largely adopted in an IoT context to provide security services such as key-exchange and digital signature. For Real-Time IoT applications, hardware acceleration for ECC-based algorithms can be mandatory to meet low-latency and low-power/energy requirements. In this paper, we propose a fast and configurable hardware accelerator for NIST P-256/-521 elliptic curves, developed in the context of the European Processor Initiative. The proposed architecture supports the most used cryptography schemes based on ECC such as Elliptic Curve Digital Signature Algorithm (ECDSA), Elliptic Curve Integrated Encryption Scheme (ECIES), Elliptic Curve Diffie-Hellman (ECDH) and Elliptic Curve Menezes-Qu-Vanstone (ECMQV). A modified version of Double-And-Add-Always algorithm for Point Multiplication has been proposed, which allows the execution of Point Addition and Doubling operations concurrently and implements countermeasures against power and timing attacks. A simulated approach to extract power traces has been used to assess the effectiveness of the proposed algorithm compared to classical algorithms for Point Multiplication. A constant-time version of the Shamir’s Trick has been adopted to speed-up the Double-Point Multiplication and modular inversion is executed using Fermat’s Little Theorem, reusing the internal modular multipliers. The accelerator has been verified on a Xilinx ZCU106 development board and synthesized on both 45 nm and 7 nm Standard-Cell technologies.

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Cryptographically Secure Pseudo-Random Number Generator IP-Core Based on SHA2 Algorithm

Cited by 27 publications

References 11 publications

True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA

Application of Resistive Random Access Memory in Hardware Security: A Review

Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications

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